[llvm] r322227 - [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 14:07:16 PST 2018
Author: ctopper
Date: Wed Jan 10 14:07:16 2018
New Revision: 322227
URL: http://llvm.org/viewvc/llvm-project?rev=322227&view=rev
Log:
[X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor
After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist.
Differential Revision: https://reviews.llvm.org/D41721
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=322227&r1=322226&r2=322227&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Jan 10 14:07:16 2018
@@ -67,19 +67,10 @@ public:
};
class X86AsmBackend : public MCAsmBackend {
- const StringRef CPU;
- bool HasNopl;
- const uint64_t MaxNopLength;
+ const MCSubtargetInfo &STI;
public:
- X86AsmBackend(const Target &T, StringRef CPU)
- : MCAsmBackend(), CPU(CPU),
- MaxNopLength((CPU == "slm" || CPU == "silvermont") ? 7 : 15) {
- HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
- CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
- CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
- CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
- CPU != "c3" && CPU != "c3-2" && CPU != "lakemont" && CPU != "";
- }
+ X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
+ : MCAsmBackend(), STI(STI) {}
unsigned getNumFixupKinds() const override {
return X86::NumTargetFixupKinds;
@@ -346,14 +337,15 @@ bool X86AsmBackend::writeNopData(uint64_
};
// This CPU doesn't support long nops. If needed add more.
- // FIXME: Can we get this from the subtarget somehow?
// FIXME: We could generated something better than plain 0x90.
- if (!HasNopl) {
+ if (!STI.getFeatureBits()[X86::FeatureNOPL]) {
for (uint64_t i = 0; i < Count; ++i)
OW->write8(0x90);
return true;
}
+ uint64_t MaxNopLength = STI.getFeatureBits()[X86::ProcIntelSLM] ? 7 : 15;
+
// 15 is the longest single nop instruction. Emit as many 15-byte nops as
// needed, then emit a nop of the remaining length.
do {
@@ -377,14 +369,15 @@ namespace {
class ELFX86AsmBackend : public X86AsmBackend {
public:
uint8_t OSABI;
- ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
- : X86AsmBackend(T, CPU), OSABI(OSABI) {}
+ ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
+ : X86AsmBackend(T, STI), OSABI(OSABI) {}
};
class ELFX86_32AsmBackend : public ELFX86AsmBackend {
public:
- ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
- : ELFX86AsmBackend(T, OSABI, CPU) {}
+ ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
+ const MCSubtargetInfo &STI)
+ : ELFX86AsmBackend(T, OSABI, STI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -394,8 +387,9 @@ public:
class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
public:
- ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
- : ELFX86AsmBackend(T, OSABI, CPU) {}
+ ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
+ const MCSubtargetInfo &STI)
+ : ELFX86AsmBackend(T, OSABI, STI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -406,8 +400,9 @@ public:
class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
public:
- ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
- : ELFX86AsmBackend(T, OSABI, CPU) {}
+ ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
+ const MCSubtargetInfo &STI)
+ : ELFX86AsmBackend(T, OSABI, STI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -418,8 +413,9 @@ public:
class ELFX86_64AsmBackend : public ELFX86AsmBackend {
public:
- ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
- : ELFX86AsmBackend(T, OSABI, CPU) {}
+ ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
+ const MCSubtargetInfo &STI)
+ : ELFX86AsmBackend(T, OSABI, STI) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -431,8 +427,9 @@ class WindowsX86AsmBackend : public X86A
bool Is64Bit;
public:
- WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
- : X86AsmBackend(T, CPU)
+ WindowsX86AsmBackend(const Target &T, bool is64Bit,
+ const MCSubtargetInfo &STI)
+ : X86AsmBackend(T, STI)
, Is64Bit(is64Bit) {
}
@@ -790,9 +787,9 @@ private:
}
public:
- DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
- bool Is64Bit)
- : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
+ DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
+ const MCSubtargetInfo &STI, bool Is64Bit)
+ : X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) {
memset(SavedRegs, 0, sizeof(SavedRegs));
OffsetSize = Is64Bit ? 8 : 4;
MoveInstrSize = Is64Bit ? 3 : 2;
@@ -803,8 +800,8 @@ public:
class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
public:
DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
- StringRef CPU)
- : DarwinX86AsmBackend(T, MRI, CPU, false) {}
+ const MCSubtargetInfo &STI)
+ : DarwinX86AsmBackend(T, MRI, STI, false) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -824,8 +821,8 @@ class DarwinX86_64AsmBackend : public Da
const MachO::CPUSubTypeX86 Subtype;
public:
DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
- StringRef CPU, MachO::CPUSubTypeX86 st)
- : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
+ const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st)
+ : DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -847,19 +844,18 @@ MCAsmBackend *llvm::createX86_32AsmBacke
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
- StringRef CPU = STI.getCPU();
if (TheTriple.isOSBinFormatMachO())
- return new DarwinX86_32AsmBackend(T, MRI, CPU);
+ return new DarwinX86_32AsmBackend(T, MRI, STI);
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
- return new WindowsX86AsmBackend(T, false, CPU);
+ return new WindowsX86AsmBackend(T, false, STI);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
if (TheTriple.isOSIAMCU())
- return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
+ return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
- return new ELFX86_32AsmBackend(T, OSABI, CPU);
+ return new ELFX86_32AsmBackend(T, OSABI, STI);
}
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
@@ -867,21 +863,20 @@ MCAsmBackend *llvm::createX86_64AsmBacke
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
- StringRef CPU = STI.getCPU();
if (TheTriple.isOSBinFormatMachO()) {
MachO::CPUSubTypeX86 CS =
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
.Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
.Default(MachO::CPU_SUBTYPE_X86_64_ALL);
- return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
+ return new DarwinX86_64AsmBackend(T, MRI, STI, CS);
}
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
- return new WindowsX86AsmBackend(T, true, CPU);
+ return new WindowsX86AsmBackend(T, true, STI);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
if (TheTriple.getEnvironment() == Triple::GNUX32)
- return new ELFX86_X32AsmBackend(T, OSABI, CPU);
- return new ELFX86_64AsmBackend(T, OSABI, CPU);
+ return new ELFX86_X32AsmBackend(T, OSABI, STI);
+ return new ELFX86_64AsmBackend(T, OSABI, STI);
}
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=322227&r1=322226&r2=322227&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Wed Jan 10 14:07:16 2018
@@ -34,6 +34,9 @@ def Mode16Bit : SubtargetFeature<"16bit-
def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
"Enable X87 float instructions">;
+def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",
+ "Enable NOPL instruction">;
+
def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
"Enable conditional move instructions">;
@@ -390,16 +393,16 @@ def : Proc<"i586", [FeatureX8
def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
-foreach P = ["i686", "pentiumpro"] in {
- def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
-}
+def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
+def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
+ FeatureNOPL]>;
def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureCMOV, FeatureFXSR]>;
+ FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
foreach P = ["pentium3", "pentium3m"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
- FeatureFXSR]>;
+ FeatureFXSR, FeatureNOPL]>;
}
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
@@ -414,12 +417,12 @@ foreach P = ["pentium3", "pentium3m"] in
def : ProcessorModel<"pentium-m", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR]>;
+ FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
foreach P = ["pentium4", "pentium4m"] in {
def : ProcessorModel<P, GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR]>;
+ FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
}
// Intel Quark.
@@ -428,18 +431,19 @@ def : Proc<"lakemont", []>;
// Intel Core Duo.
def : ProcessorModel<"yonah", SandyBridgeModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
- FeatureFXSR]>;
+ FeatureFXSR, FeatureNOPL]>;
// NetBurst.
def : ProcessorModel<"prescott", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
- FeatureFXSR]>;
+ FeatureFXSR, FeatureNOPL]>;
def : ProcessorModel<"nocona", GenericPostRAModel, [
FeatureX87,
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE3,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B
]>;
@@ -450,6 +454,7 @@ def : ProcessorModel<"core2", SandyBridg
FeatureMMX,
FeatureSSSE3,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeatureLAHFSAHF,
FeatureMacroFusion
@@ -460,6 +465,7 @@ def : ProcessorModel<"penryn", SandyBrid
FeatureMMX,
FeatureSSE41,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeatureLAHFSAHF,
FeatureMacroFusion
@@ -473,6 +479,7 @@ class BonnellProc<string Name> : Process
FeatureMMX,
FeatureSSSE3,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeatureLEAForSP,
@@ -492,6 +499,7 @@ class SilvermontProc<string Name> : Proc
FeatureMMX,
FeatureSSE42,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
@@ -514,6 +522,7 @@ class GoldmontProc<string Name> : Proces
FeatureMMX,
FeatureSSE42,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
@@ -543,6 +552,7 @@ class NehalemProc<string Name> : Process
FeatureMMX,
FeatureSSE42,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureLAHFSAHF,
@@ -558,6 +568,7 @@ class WestmereProc<string Name> : Proces
FeatureMMX,
FeatureSSE42,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureAES,
@@ -584,6 +595,7 @@ def SNBFeatures : ProcessorFeatures<[],
FeatureMMX,
FeatureAVX,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureAES,
@@ -757,27 +769,28 @@ def : Proc<"k6-2", [FeatureX8
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
foreach P = ["athlon", "athlon-tbird"] in {
- def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowSHLD]>;
+ def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
+ FeatureNOPL, FeatureSlowSHLD]>;
}
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
+ Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
}
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- FeatureFXSR, Feature64Bit, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD]>;
}
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
}
foreach P = ["amdfam10", "barcelona"] in {
def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
- FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
FeatureSlowSHLD, FeatureLAHFSAHF]>;
}
@@ -788,6 +801,7 @@ def : Proc<"btver1", [
FeatureSSSE3,
FeatureSSE4A,
FeatureFXSR,
+ FeatureNOPL,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureLZCNT,
@@ -802,6 +816,7 @@ def : ProcessorModel<"btver2", BtVer2Mod
FeatureMMX,
FeatureAVX,
FeatureFXSR,
+ FeatureNOPL,
FeatureSSE4A,
FeatureCMPXCHG16B,
FeaturePRFCHW,
@@ -832,6 +847,7 @@ def : Proc<"bdver1", [
FeatureMMX,
FeatureAVX,
FeatureFXSR,
+ FeatureNOPL,
FeatureSSE4A,
FeatureLZCNT,
FeaturePOPCNT,
@@ -853,6 +869,7 @@ def : Proc<"bdver2", [
FeatureMMX,
FeatureAVX,
FeatureFXSR,
+ FeatureNOPL,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
@@ -879,6 +896,7 @@ def : Proc<"bdver3", [
FeatureMMX,
FeatureAVX,
FeatureFXSR,
+ FeatureNOPL,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
@@ -901,6 +919,7 @@ def : Proc<"bdver4", [
FeatureMMX,
FeatureAVX2,
FeatureFXSR,
+ FeatureNOPL,
FeatureXOP,
FeatureFMA4,
FeatureCMPXCHG16B,
@@ -938,6 +957,7 @@ def: ProcessorModel<"znver1", Znver1Mode
FeatureFMA,
FeatureFSGSBase,
FeatureFXSR,
+ FeatureNOPL,
FeatureFastLZCNT,
FeatureLAHFSAHF,
FeatureLZCNT,
@@ -982,6 +1002,7 @@ def : ProcessorModel<"x86-64", SandyBrid
FeatureMMX,
FeatureSSE2,
FeatureFXSR,
+ FeatureNOPL,
Feature64Bit,
FeatureSlow3OpsLEA,
FeatureSlowIncDec,
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=322227&r1=322226&r2=322227&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Jan 10 14:07:16 2018
@@ -260,6 +260,7 @@ void X86Subtarget::initializeEnvironment
X86SSELevel = NoSSE;
X863DNowLevel = NoThreeDNow;
HasX87 = false;
+ HasNOPL = false;
HasCMov = false;
HasX86_64 = false;
HasPOPCNT = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=322227&r1=322226&r2=322227&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Wed Jan 10 14:07:16 2018
@@ -92,6 +92,10 @@ protected:
/// True if the processor supports X87 instructions.
bool HasX87;
+ /// True if this processor has NOPL instruction
+ /// (generally pentium pro+).
+ bool HasNOPL;
+
/// True if this processor has conditional move instructions
/// (generally pentium pro+).
bool HasCMov;
@@ -469,6 +473,7 @@ public:
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
bool hasX87() const { return HasX87; }
+ bool hasNOPL() const { return HasNOPL; }
bool hasCMov() const { return HasCMov; }
bool hasSSE1() const { return X86SSELevel >= SSE1; }
bool hasSSE2() const { return X86SSELevel >= SSE2; }
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