[llvm] r322218 - [RISCV] Add support for llvm.{frameaddress, returnaddress} intrinsics
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 12:12:01 PST 2018
Author: asb
Date: Wed Jan 10 12:12:00 2018
New Revision: 322218
URL: http://llvm.org/viewvc/llvm-project?rev=322218&view=rev
Log:
[RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics
Added:
llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=322218&r1=322217&r2=322218&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Wed Jan 10 12:12:00 2018
@@ -166,6 +166,10 @@ SDValue RISCVTargetLowering::LowerOperat
return lowerSELECT(Op, DAG);
case ISD::VASTART:
return lowerVASTART(Op, DAG);
+ case ISD::FRAMEADDR:
+ return LowerFRAMEADDR(Op, DAG);
+ case ISD::RETURNADDR:
+ return LowerRETURNADDR(Op, DAG);
}
}
@@ -284,6 +288,59 @@ SDValue RISCVTargetLowering::lowerVASTAR
MachinePointerInfo(SV));
}
+SDValue RISCVTargetLowering::LowerFRAMEADDR(SDValue Op,
+ SelectionDAG &DAG) const {
+ const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ MFI.setFrameAddressIsTaken(true);
+ unsigned FrameReg = RI.getFrameRegister(MF);
+ int XLenInBytes = Subtarget.getXLen() / 8;
+
+ EVT VT = Op.getValueType();
+ SDLoc DL(Op);
+ SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
+ unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+ while (Depth--) {
+ int Offset = -(XLenInBytes * 2);
+ SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
+ DAG.getIntPtrConstant(Offset, DL));
+ FrameAddr =
+ DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
+ }
+ return FrameAddr;
+}
+
+SDValue RISCVTargetLowering::LowerRETURNADDR(SDValue Op,
+ SelectionDAG &DAG) const {
+ const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ MFI.setReturnAddressIsTaken(true);
+ MVT XLenVT = Subtarget.getXLenVT();
+ int XLenInBytes = Subtarget.getXLen() / 8;
+
+ if (verifyReturnAddressArgumentIsConstant(Op, DAG))
+ return SDValue();
+
+ EVT VT = Op.getValueType();
+ SDLoc DL(Op);
+ unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+ if (Depth) {
+ int Off = -XLenInBytes;
+ SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
+ SDValue Offset = DAG.getConstant(Off, DL, VT);
+ return DAG.getLoad(VT, DL, DAG.getEntryNode(),
+ DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
+ MachinePointerInfo());
+ }
+
+ // Return the value of the return address register, marking it an implicit
+ // live-in.
+ unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
+ return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
+}
+
MachineBasicBlock *
RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const {
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=322218&r1=322217&r2=322218&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Wed Jan 10 12:12:00 2018
@@ -83,6 +83,8 @@ private:
SDValue lowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
};
}
Added: llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll?rev=322218&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll Wed Jan 10 12:12:00 2018
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+
+declare void @notdead(i8*)
+declare i8* @llvm.frameaddress(i32)
+declare i8* @llvm.returnaddress(i32)
+
+define i8* @test_frameaddress_0() nounwind {
+; RV32I-LABEL: test_frameaddress_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: addi s0, sp, 16
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+ %1 = call i8* @llvm.frameaddress(i32 0)
+ ret i8* %1
+}
+
+define i8* @test_frameaddress_2() nounwind {
+; RV32I-LABEL: test_frameaddress_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: addi s0, sp, 16
+; RV32I-NEXT: lw a0, -8(s0)
+; RV32I-NEXT: lw a0, -8(a0)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+ %1 = call i8* @llvm.frameaddress(i32 2)
+ ret i8* %1
+}
+
+define i8* @test_frameaddress_3_alloca() nounwind {
+; RV32I-LABEL: test_frameaddress_3_alloca:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -112
+; RV32I-NEXT: sw ra, 108(sp)
+; RV32I-NEXT: sw s0, 104(sp)
+; RV32I-NEXT: addi s0, sp, 112
+; RV32I-NEXT: lui a0, %hi(notdead)
+; RV32I-NEXT: addi a1, a0, %lo(notdead)
+; RV32I-NEXT: addi a0, s0, -108
+; RV32I-NEXT: jalr a1
+; RV32I-NEXT: lw a0, -8(s0)
+; RV32I-NEXT: lw a0, -8(a0)
+; RV32I-NEXT: lw a0, -8(a0)
+; RV32I-NEXT: lw s0, 104(sp)
+; RV32I-NEXT: lw ra, 108(sp)
+; RV32I-NEXT: addi sp, sp, 112
+; RV32I-NEXT: ret
+ %1 = alloca [100 x i8]
+ %2 = bitcast [100 x i8]* %1 to i8*
+ call void @notdead(i8* %2)
+ %3 = call i8* @llvm.frameaddress(i32 3)
+ ret i8* %3
+}
+
+define i8* @test_returnaddress_0() nounwind {
+; RV32I-LABEL: test_returnaddress_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: addi s0, sp, 16
+; RV32I-NEXT: mv a0, ra
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+ %1 = call i8* @llvm.returnaddress(i32 0)
+ ret i8* %1
+}
+
+define i8* @test_returnaddress_2() nounwind {
+; RV32I-LABEL: test_returnaddress_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: addi s0, sp, 16
+; RV32I-NEXT: lw a0, -8(s0)
+; RV32I-NEXT: lw a0, -8(a0)
+; RV32I-NEXT: lw a0, -4(a0)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+ %1 = call i8* @llvm.returnaddress(i32 2)
+ ret i8* %1
+}
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