[PATCH] D41900: [AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: lib/Target/AArch64/SVEInstrFormats.td:100
+class sve_int_read_vl_a<bits<6> opc, string asm>
+: I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
+  asm, "\t$Rd, $imm6",
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I think it is clearer to split this up in 2 operands: op and opc2, which then matches with the "encoding group".


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Comment at: test/MC/AArch64/SVE/rdvl-diagnostics.s:4
+// Immediate out of upper bound [-32, 31].
+rdvl x9, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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Perhaps a nice to have, test that it doesn't accept a register operand as the 2nd operand?


https://reviews.llvm.org/D41900