[PATCH] D41905: [ARM] Add support for unpredictable MVN instructions.

[Yvan Roux via Phabricator via llvm-commits]

yroux created this revision.
Herald added subscribers: javed.absar, aemerson.

This fixes bugzilla 33011
https://bugs.llvm.org/show_bug.cgi?id=33011

Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in
sections A8.8.116 and A8.8.117.

It fixes also the usage of PC register as destination register for MVN
register-shifted register version as specified in A8.8.117.

Validated with regression testsuite passed without regression.


https://reviews.llvm.org/D41905

Files:
  lib/Target/ARM/ARMInstrInfo.td
  test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt


Index: test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x03 0x20 0xe1 0xe1
+0x03 0x20 0xe1 0xe1
+
+# CHECK: potentially undefined
+# CHECK: 0x1f 0x57 0xe0 0xe1
+0x1f 0x57 0xe0 0xe1
+
+# CHECK: potentially undefined
+# CHECK: 0x16 0xf7 0xe0 0xe1
+0x16 0xf7 0xe0 0xe1
+
+# CHECK: potentially undefined
+# CHECK: 0x16 0x5f 0xe0 0xe1
+0x16 0x5f 0xe0 0xe1
Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -3904,6 +3904,8 @@
   let Inst{11-4} = 0b00000000;
   let Inst{15-12} = Rd;
   let Inst{3-0} = Rm;
+
+  let Unpredictable{19-16} = 0b1111;
 }
 def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
                   DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
@@ -3917,10 +3919,12 @@
   let Inst{11-5} = shift{11-5};
   let Inst{4} = 0;
   let Inst{3-0} = shift{3-0};
+
+  let Unpredictable{19-16} = 0b1111;
 }
-def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
+def  MVNsr  : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
                   DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
-                  [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
+                  [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
                   Sched<[WriteALU]> {
   bits<4> Rd;
   bits<12> shift;
@@ -3932,6 +3936,8 @@
   let Inst{6-5} = shift{6-5};
   let Inst{4} = 1;
   let Inst{3-0} = shift{3-0};
+
+  let Unpredictable{19-16} = 0b1111;
 }
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,


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