[llvm] r322170 - [ARM GlobalISel] Add inst selector tests for G_FNEG s32 and s64
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 10 03:13:36 PST 2018
Author: rovka
Date: Wed Jan 10 03:13:36 2018
New Revision: 322170
URL: http://llvm.org/viewvc/llvm-project?rev=322170&view=rev
Log:
[ARM GlobalISel] Add inst selector tests for G_FNEG s32 and s64
G_FNEG is already handled by the TableGen'erated code. Just add a few
tests to make sure everything works as expected.
Modified:
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir?rev=322170&r1=322169&r2=322170&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir Wed Jan 10 03:13:36 2018
@@ -30,9 +30,14 @@
define void @test_movti16_0xffff() #2 { ret void }
+ define void @test_vnmuls() #3 { ret void }
+ define void @test_vnmuls_reassociate() #3 { ret void }
+ define void @test_vnmuld() #3 { ret void }
+
attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="-v6" }
attributes #2 = { "target-features"="+v6t2" }
+ attributes #3 = { "target-features"="+vfp2" }
...
---
name: test_mla
@@ -863,3 +868,96 @@ body: |
BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
+---
+name: test_vnmuls
+# CHECK-LABEL: name: test_vnmuls
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+ - { id: 3, class: fprb }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+ %2(s32) = G_FMUL %0, %1
+ %3(s32) = G_FNEG %2
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+
+ %s0 = COPY %3(s32)
+ ; CHECK: %s0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %s0
+ ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_vnmuls_reassociate
+# CHECK-LABEL: name: test_vnmuls_reassociate
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+ - { id: 3, class: fprb }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+ %2(s32) = G_FNEG %0
+ %3(s32) = G_FMUL %1, %2
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+
+ %s0 = COPY %3(s32)
+ ; CHECK: %s0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %s0
+ ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_vnmuld
+# CHECK-LABEL: name: test_vnmuld
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+ - { id: 3, class: fprb }
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+
+ %2(s64) = G_FMUL %0, %1
+ %3(s64) = G_FNEG %2
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, %noreg
+
+ %d0 = COPY %3(s64)
+ ; CHECK: %d0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %d0
+ ; CHECK: BX_RET 14, %noreg, implicit %d0
+...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=322170&r1=322169&r2=322170&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Wed Jan 10 03:13:36 2018
@@ -24,6 +24,9 @@
define void @test_fdiv_s32() #0 { ret void }
define void @test_fdiv_s64() #0 { ret void }
+ define void @test_fneg_s32() #0 { ret void }
+ define void @test_fneg_s64() #0 { ret void }
+
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
@@ -605,6 +608,59 @@ body: |
; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, %noreg, implicit %d0
+ ; CHECK: BX_RET 14, %noreg, implicit %d0
+...
+---
+name: test_fneg_s32
+# CHECK-LABEL: name: test_fneg_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+
+ %1(s32) = G_FNEG %0
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, %noreg
+
+ %s0 = COPY %1(s32)
+ ; CHECK: %s0 = COPY [[VREGSUM]]
+
+ BX_RET 14, %noreg, implicit %s0
+ ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_fneg_s64
+# CHECK-LABEL: name: test_fneg_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+
+ %1(s64) = G_FNEG %0
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, %noreg
+
+ %d0 = COPY %1(s64)
+ ; CHECK: %d0 = COPY [[VREGSUM]]
+
+ BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, %noreg, implicit %d0
...
---
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