[llvm] r322164 - [ARM GlobalISel] Legalize s32/s64 G_FCONSTANT

[Diana Picus via llvm-commits]

Author: rovka
Date: Wed Jan 10 02:01:49 2018
New Revision: 322164

URL: http://llvm.org/viewvc/llvm-project?rev=322164&view=rev
Log:
[ARM GlobalISel] Legalize s32/s64 G_FCONSTANT

Legal for hard float.
Change to G_CONSTANT for soft float (but preserve the binary
representation).

Modified:
    llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=322164&r1=322163&r2=322164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Wed Jan 10 02:01:49 2018
@@ -161,7 +161,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
     setAction({G_ICMP, 1, Ty}, Legal);
 
   if (!ST.useSoftFloat() && ST.hasVFP2()) {
-    for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
+    for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT})
       for (auto Ty : {s32, s64})
         setAction({BinOp, Ty}, Legal);
 
@@ -183,6 +183,10 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
       for (auto Ty : {s32, s64})
         setAction({BinOp, Ty}, Libcall);
 
+    for (auto Ty : {s32, s64}) {
+      setAction({G_FCONSTANT, Ty}, Custom);
+    }
+
     setAction({G_FCMP, s1}, Legal);
     setAction({G_FCMP, 1, s32}, Custom);
     setAction({G_FCMP, 1, s64}, Custom);
@@ -313,6 +317,7 @@ bool ARMLegalizerInfo::legalizeCustom(Ma
   using namespace TargetOpcode;
 
   MIRBuilder.setInstr(MI);
+  LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
 
   switch (MI.getOpcode()) {
   default:
@@ -329,7 +334,6 @@ bool ARMLegalizerInfo::legalizeCustom(Ma
 
     // Our divmod libcalls return a struct containing the quotient and the
     // remainder. We need to create a virtual register for it.
-    auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
     Type *ArgTy = Type::getInt32Ty(Ctx);
     StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
     auto RetVal = MRI.createGenericVirtualRegister(
@@ -370,7 +374,6 @@ bool ARMLegalizerInfo::legalizeCustom(Ma
       return true;
     }
 
-    auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
     assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
     auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
     auto *RetTy = Type::getInt32Ty(Ctx);
@@ -415,6 +418,14 @@ bool ARMLegalizerInfo::legalizeCustom(Ma
     }
     break;
   }
+  case G_FCONSTANT: {
+    // Convert to integer constants, while preserving the binary representation.
+    auto AsInteger =
+        MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
+    MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
+                             *ConstantInt::get(Ctx, AsInteger));
+    break;
+  }
   }
 
   MI.eraseFromParent();

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=322164&r1=322163&r2=322164&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Wed Jan 10 02:01:49 2018
@@ -20,6 +20,9 @@
   define void @test_fdiv_float() { ret void }
   define void @test_fdiv_double() { ret void }
 
+  define void @test_fconstant_float() { ret void }
+  define void @test_fconstant_double() { ret void }
+
   define void @test_fcmp_true_s32() { ret void }
   define void @test_fcmp_false_s32() { ret void }
 
@@ -597,6 +600,59 @@ body:             |
     BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
+name:            test_fconstant_float
+# CHECK-LABEL: name: test_fconstant_float
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+body:             |
+  bb.0:
+    liveins:
+
+    ; HARD: [[R:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.25
+    ; SOFT-NOT: G_FCONSTANT
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1080033280
+    ; SOFT-NOT: G_FCONSTANT
+    %0(s32) = G_FCONSTANT float -1.25
+    ; CHECK: %r0 = COPY [[R]]
+    %r0 = COPY %0(s32)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
+name:            test_fconstant_double
+# CHECK-LABEL: name: test_fconstant_double
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins:
+
+    ; HARD: [[R:%[0-9]+]]:_(s64) = G_FCONSTANT double -2.4
+    ; SOFT-NOT: G_FCONSTANT
+    ; SOFT-DAG: [[HI:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073532109
+    ; SOFT-DAG: [[LO:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
+    ; SOFT-NOT: G_FCONSTANT
+    %0(s64) = G_FCONSTANT double -2.4
+    ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+    ; SOFT-DAG: %r0 = COPY [[HI]]
+    ; SOFT-DAG: %r1 = COPY [[LO]]
+    %1(s32),%2(s32) = G_UNMERGE_VALUES %0(s64)
+    %r0 = COPY %2(s32)
+    %r1 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
+...
+---
 name:            test_fcmp_true_s32
 # CHECK-LABEL: name: test_fcmp_true_s32
 legalized:       false