[PATCH] D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 10 01:57:46 PST 2018


SjoerdMeijer added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:736
+    AddPromotedToType(ISD::STORE, VT, MVT::v4i16);
   } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
     setOperationAction(ISD::LOAD, VT, Promote);
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How about MVT::v8f16? Does this one needs to get a similar treatment?


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Comment at: lib/Target/AArch64/AArch64InstrInfo.td:5852
 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
-                             (v4f16 (REV64v4i16 FPR64:$src))>;
+                             (v4f16 FPR64:$src)>;
 def : Pat<(v4f16 (bitconvert (v8i8  FPR64:$src))),
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Don't think I understand why this is now a special case. Why is this one different from the other patterns here?


https://reviews.llvm.org/D41863





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