[llvm] r322120 - [SelectionDAG] Fixed f16-from-vector promotion problem
Tim Renouf via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 9 13:36:25 PST 2018
Author: tpr
Date: Tue Jan 9 13:36:25 2018
New Revision: 322120
URL: http://llvm.org/viewvc/llvm-project?rev=322120&view=rev
Log:
[SelectionDAG] Fixed f16-from-vector promotion problem
Summary:
In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the
result of a bitcast from i16, avoid creating an illegal fp16_to_fp where
the input is not a vector and the result is a v1f32.
V2: The fix is now to avoid vector scalarization creating a v1->scalar
bitcast.
Reviewers: srhines, t.p.northover
Subscribers: nhaehnle, llvm-commits, dstuttard, t-tye, yaxunl, wdng, kzhuravl, arsenm
Differential Revision: https://reviews.llvm.org/D41126
Added:
llvm/trunk/test/CodeGen/AMDGPU/unpack-half.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=322120&r1=322119&r2=322120&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jan 9 13:36:25 2018
@@ -169,9 +169,15 @@ SDValue DAGTypeLegalizer::ScalarizeVecRe
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
+ SDValue Op = N->getOperand(0);
+ if (Op.getValueType().isVector()
+ && Op.getValueType().getVectorNumElements() == 1) {
+ assert(!isSimpleLegalType(Op.getValueType()));
+ Op = GetScalarizedVector(Op);
+ }
EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BITCAST, SDLoc(N),
- NewVT, N->getOperand(0));
+ NewVT, Op);
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
Added: llvm/trunk/test/CodeGen/AMDGPU/unpack-half.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unpack-half.ll?rev=322120&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/unpack-half.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/unpack-half.ll Tue Jan 9 13:36:25 2018
@@ -0,0 +1,26 @@
+; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s
+
+; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the
+; extension of a vector of f16 generates an illegal node that errors later.
+
+; CHECK-LABEL: {{^}}main:
+; CHECK: v_cvt_f32_f16
+
+define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 {
+.entry:
+ %tmp = load volatile float, float addrspace(1)* undef
+ %tmp1 = bitcast float %tmp to i32
+ %im0.i = lshr i32 %tmp1, 16
+ %tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1
+ %tmp3 = trunc <2 x i32> %tmp2 to <2 x i16>
+ %tmp4 = bitcast <2 x i16> %tmp3 to <2 x half>
+ %tmp5 = fpext <2 x half> %tmp4 to <2 x float>
+ %bc = bitcast <2 x float> %tmp5 to <2 x i32>
+ %tmp6 = extractelement <2 x i32> %bc, i32 1
+ store volatile i32 %tmp6, i32 addrspace(1)* undef
+ ret void
+}
+
+attributes #0 = { nounwind }
+
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