[PATCH] D41811: X86: Add pattern matching for PMADDWD
Zvi Rackover via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 9 12:09:28 PST 2018
zvi added inline comments.
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:37062
+ SDValue Op, ArrayRef<unsigned> ExpectedIndices, SDValue &RetMul) {
+ if (Op->getOpcode() != ISD::BUILD_VECTOR)
+ return false;
----------------
craig.topper wrote:
> What ensures the multiply has exactly 2X the elements of the build_vector? Couldn't it have more? Which would cause the truncate later to fail.
You're right! Will fix and add tests
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:37087
+ SDValue L, R;
+ const unsigned ExpectedEvenIndices[] = {0, 2, 4, 6, 8, 10, 12, 14,
+ 16, 18, 20, 22, 24, 26, 28, 30};
----------------
craig.topper wrote:
> Is there anything that guarantees even indices will be on the LHS?
Will add checks for both orderings. thanks
https://reviews.llvm.org/D41811
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