[PATCH] D41821: [MIPS] Disassemble the 0xefefefef trap padding used by LLD

[Simon Dardis via Phabricator via llvm-commits]

sdardis added a comment.

> Right now I do not know why llvm-objdump does not show a correct instruction instead of "<unknown>". By the way GNU objdump shows "swc3 $15,-4113(ra)" for "efefefef".

It's not being disassembled as the disassembler sets the internal state to be mips32. The COP3 opcodes are only disassembled for MIPS-I and MIPS-II.

That opcode was repurposed in MIPSR6:

8:	efefefef 	lwpc	ra,0xffffbfc4

For micromips(r6):

  10:	ef ef 	li16	$7, 111

Which is not particularly useful as trap instructions.

I'm a little uncertain as to what specific opcode we should use here. If we have a pure microMIPS or pure MIPS environment, we can use the corresponding 'sigrie' opcode from MIPSR6 to cause a reserved instruction trap. In revisions prior to revision 6, those instructions trap anyway.

In a mixed environment as we have a problem where we don't know what ISA mode we're operating in, so we'd have to alternate 'sigrie's as the microMIPSR6 'sigrie' corresponds to a valid MIPS64 no-op instruction and to ensure that the processor sees both if we've hit padding.

I've looked at the instruction tables and I believe that the MIPSR6 sigrie with the operand 1 is the best choice. Modulo a bug in upstream binutils, for microMIPS it disassembles to:

  0:	04 17 	subu16	$3, $16, $17
  2:	00 01  <unknown>
  4:	04 17 	subu16	$3, $16, $17
  6:	00 01  <unknown>

Which I believe is the simplest solution. That just requires a small change to lld, and providing an implementation of sigrie for MIPS in llvm.


https://reviews.llvm.org/D41821