[PATCH] D41667: [DAGCombine] Fix for PR35761

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jan 7 02:44:41 PST 2018

RKSimon added inline comments.

Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3924
+      else
+        DAG.UpdateNodeOperands(LogicN, LogicN->getOperand(1), And);
It might be clearer if you just do something like:

SDValue Op0 = LogicN->getOperand(0);
SDValue Op1 = LogicN->getOperand(1);

if (isa<ConstantSDNode>(Op0))
  std::swap(Op0, Op1);

SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), Op1, MaskOp);
DAG.UpdateNodeOperands(LogicN, Op0, And);

Comment at: test/CodeGen/X86/pr35761.ll:66
+  ret void
Please can you try to reduce this further


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