[llvm] r321939 - [X86] Remove memory forms of EVEX encoded vcvtsd2si/vcvtss2si from the assembler matcher table
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 6 11:20:34 PST 2018
Author: ctopper
Date: Sat Jan 6 11:20:33 2018
New Revision: 321939
URL: http://llvm.org/viewvc/llvm-project?rev=321939&view=rev
Log:
[X86] Remove memory forms of EVEX encoded vcvtsd2si/vcvtss2si from the assembler matcher table
We should always prefer the VEX encoded version of these instructions. There is no advantage to the EVEX version.
Fixes PR35837.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/MC/X86/avx512-encodings.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=321939&r1=321938&r2=321939&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sat Jan 6 11:20:33 2018
@@ -6456,7 +6456,9 @@ def : Pat<(f64 (uint_to_fp GR64:$src)),
multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT,
X86VectorVTInfo DstVT, SDNode OpNode,
- OpndItins itins, string asm, string aliasStr> {
+ OpndItins itins, string asm,
+ string aliasStr,
+ bit CodeGenOnly = 1> {
let Predicates = [HasAVX512] in {
def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
@@ -6467,6 +6469,7 @@ multiclass avx512_cvt_s_int_round<bits<8
[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))],
itins.rr>, EVEX, VEX_LIG, EVEX_B, EVEX_RC,
Sched<[itins.Sched]>;
+ let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in
def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set DstVT.RC:$dst, (OpNode
@@ -6478,6 +6481,15 @@ multiclass avx512_cvt_s_int_round<bits<8
(!cast<Instruction>(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0>;
def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}",
(!cast<Instruction>(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0>;
+ } // Predicates = [HasAVX512]
+}
+
+multiclass avx512_cvt_s_int_round_aliases<bits<8> opc, X86VectorVTInfo SrcVT,
+ X86VectorVTInfo DstVT, SDNode OpNode,
+ OpndItins itins, string asm,
+ string aliasStr> :
+ avx512_cvt_s_int_round<opc, SrcVT, DstVT, OpNode, itins, asm, aliasStr, 0> {
+ let Predicates = [HasAVX512] in {
def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rm_Int") DstVT.RC:$dst,
SrcVT.IntScalarMemOp:$src), 0>;
@@ -6491,10 +6503,10 @@ defm VCVTSS2SIZ: avx512_cvt_s_int_round<
defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
X86cvts2si, SSE_CVT_SS2SI_64, "cvtss2si", "{q}">,
XS, VEX_W, EVEX_CD8<32, CD8VT1>;
-defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
+defm VCVTSS2USIZ: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i32x_info,
X86cvts2usi, SSE_CVT_SS2SI_32, "cvtss2usi", "{l}">,
XS, EVEX_CD8<32, CD8VT1>;
-defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
+defm VCVTSS2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i64x_info,
X86cvts2usi, SSE_CVT_SS2SI_64, "cvtss2usi", "{q}">,
XS, VEX_W, EVEX_CD8<32, CD8VT1>;
defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
@@ -6503,10 +6515,10 @@ defm VCVTSD2SIZ: avx512_cvt_s_int_round<
defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si", "{q}">,
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
-defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
+defm VCVTSD2USIZ: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i32x_info,
X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{l}">,
XD, EVEX_CD8<64, CD8VT1>;
-defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
+defm VCVTSD2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i64x_info,
X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{q}">,
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
Modified: llvm/trunk/test/MC/X86/avx512-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=321939&r1=321938&r2=321939&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/avx512-encodings.s (original)
+++ llvm/trunk/test/MC/X86/avx512-encodings.s Sat Jan 6 11:20:33 2018
@@ -19691,7 +19691,7 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
vcvtsd2sil %xmm16, %eax
// CHECK: vcvtsd2si (%rax), %ebx
-// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x2d,0x18]
+// CHECK: encoding: [0xc5,0xfb,0x2d,0x18]
vcvtsd2sil (%rax), %ebx
// CHECK: vcvtss2si %xmm16, %eax
@@ -19699,7 +19699,7 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
vcvtss2sil %xmm16, %eax
// CHECK: vcvtss2si (%rax), %ebx
-// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x2d,0x18]
+// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
vcvtss2sil (%rax), %ebx
// CHECK: vcvtsd2si %xmm16, %rax
@@ -19707,7 +19707,7 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
vcvtsd2siq %xmm16, %rax
// CHECK: vcvtsd2si (%rax), %rbx
-// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x2d,0x18]
+// CHECK: encoding: [0xc4,0xe1,0xfb,0x2d,0x18]
vcvtsd2siq (%rax), %rbx
// CHECK: vcvtss2si %xmm16, %rax
@@ -19715,7 +19715,7 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
vcvtss2siq %xmm16, %rax
// CHECK: vcvtss2si (%rax), %rbx
-// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x2d,0x18]
+// CHECK: encoding: [0xc4,0xe1,0xfa,0x2d,0x18]
vcvtss2siq (%rax), %rbx
// CHECK: vcvtsd2usi %xmm16, %eax
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