[llvm] r321912 - [X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 5 15:13:54 PST 2018
Author: ctopper
Date: Fri Jan 5 15:13:54 2018
New Revision: 321912
URL: http://llvm.org/viewvc/llvm-project?rev=321912&view=rev
Log:
[X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded instructions.
This matches their VEX equivalents.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/MC/X86/avx512-encodings.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=321912&r1=321911&r2=321912&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Fri Jan 5 15:13:54 2018
@@ -6456,7 +6456,7 @@ def : Pat<(f64 (uint_to_fp GR64:$src)),
multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT,
X86VectorVTInfo DstVT, SDNode OpNode,
- OpndItins itins, string asm> {
+ OpndItins itins, string asm, string aliasStr> {
let Predicates = [HasAVX512] in {
def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
@@ -6473,33 +6473,41 @@ multiclass avx512_cvt_s_int_round<bits<8
(SrcVT.VT SrcVT.ScalarIntMemCPat:$src),
(i32 FROUND_CURRENT)))], itins.rm>,
EVEX, VEX_LIG, Sched<[itins.Sched.Folded, ReadAfterLd]>;
+
+ def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0>;
+ def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}",
+ (!cast<Instruction>(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0>;
+ def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "rm_Int") DstVT.RC:$dst,
+ SrcVT.IntScalarMemOp:$src), 0>;
} // Predicates = [HasAVX512]
}
// Convert float/double to signed/unsigned int 32/64
defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
- X86cvts2si, SSE_CVT_SS2SI_32, "cvtss2si">,
+ X86cvts2si, SSE_CVT_SS2SI_32, "cvtss2si", "{l}">,
XS, EVEX_CD8<32, CD8VT1>;
defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
- X86cvts2si, SSE_CVT_SS2SI_64, "cvtss2si">,
+ X86cvts2si, SSE_CVT_SS2SI_64, "cvtss2si", "{q}">,
XS, VEX_W, EVEX_CD8<32, CD8VT1>;
defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
- X86cvts2usi, SSE_CVT_SS2SI_32, "cvtss2usi">,
+ X86cvts2usi, SSE_CVT_SS2SI_32, "cvtss2usi", "{l}">,
XS, EVEX_CD8<32, CD8VT1>;
defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
- X86cvts2usi, SSE_CVT_SS2SI_64, "cvtss2usi">,
+ X86cvts2usi, SSE_CVT_SS2SI_64, "cvtss2usi", "{q}">,
XS, VEX_W, EVEX_CD8<32, CD8VT1>;
defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
- X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si">,
+ X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si", "{l}">,
XD, EVEX_CD8<64, CD8VT1>;
defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
- X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si">,
+ X86cvts2si, SSE_CVT_SD2SI, "cvtsd2si", "{q}">,
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
- X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi">,
+ X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{l}">,
XD, EVEX_CD8<64, CD8VT1>;
defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
- X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi">,
+ X86cvts2usi, SSE_CVT_SD2SI, "cvtsd2usi", "{q}">,
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
// The SSE version of these instructions are disabled for AVX512.
@@ -6590,7 +6598,7 @@ let Predicates = [HasAVX512] in {
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
- def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}",
+ def : InstAlias<asm # aliasStr # "\t{{sae}, $src, $dst|$dst, $src, {sae}}",
(!cast<Instruction>(NAME # "rrb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst,
Modified: llvm/trunk/test/MC/X86/avx512-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=321912&r1=321911&r2=321912&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/avx512-encodings.s (original)
+++ llvm/trunk/test/MC/X86/avx512-encodings.s Fri Jan 5 15:13:54 2018
@@ -19685,3 +19685,67 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
// CHECK: vmovq %xmm31, %rax
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7e,0xf8]
vmovd %xmm31, %rax
+
+// CHECK: vcvtsd2si %xmm16, %eax
+// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x2d,0xc0]
+ vcvtsd2sil %xmm16, %eax
+
+// CHECK: vcvtsd2si (%rax), %ebx
+// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x2d,0x18]
+ vcvtsd2sil (%rax), %ebx
+
+// CHECK: vcvtss2si %xmm16, %eax
+// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x2d,0xc0]
+ vcvtss2sil %xmm16, %eax
+
+// CHECK: vcvtss2si (%rax), %ebx
+// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x2d,0x18]
+ vcvtss2sil (%rax), %ebx
+
+// CHECK: vcvtsd2si %xmm16, %rax
+// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x2d,0xc0]
+ vcvtsd2siq %xmm16, %rax
+
+// CHECK: vcvtsd2si (%rax), %rbx
+// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x2d,0x18]
+ vcvtsd2siq (%rax), %rbx
+
+// CHECK: vcvtss2si %xmm16, %rax
+// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x2d,0xc0]
+ vcvtss2siq %xmm16, %rax
+
+// CHECK: vcvtss2si (%rax), %rbx
+// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x2d,0x18]
+ vcvtss2siq (%rax), %rbx
+
+// CHECK: vcvtsd2usi %xmm16, %eax
+// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x79,0xc0]
+ vcvtsd2usil %xmm16, %eax
+
+// CHECK: vcvtsd2usi (%rax), %ebx
+// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x79,0x18]
+ vcvtsd2usil (%rax), %ebx
+
+// CHECK: vcvtss2usi %xmm16, %eax
+// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x79,0xc0]
+ vcvtss2usil %xmm16, %eax
+
+// CHECK: vcvtss2usi (%rax), %ebx
+// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x79,0x18]
+ vcvtss2usil (%rax), %ebx
+
+// CHECK: vcvtsd2usi %xmm16, %rax
+// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x79,0xc0]
+ vcvtsd2usiq %xmm16, %rax
+
+// CHECK: vcvtsd2usi (%rax), %rbx
+// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x79,0x18]
+ vcvtsd2usiq (%rax), %rbx
+
+// CHECK: vcvtss2usi %xmm16, %rax
+// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x79,0xc0]
+ vcvtss2usiq %xmm16, %rax
+
+// CHECK: vcvtss2usi (%rax), %rbx
+// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x79,0x18]
+ vcvtss2usiq (%rax), %rbx
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