[PATCH] D40805: [RISCV] Support for varargs

Leslie Zhai via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 4 19:22:23 PST 2018

xiangzhai added inline comments.

Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:446
+    unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
+    if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) {
+      State.AllocateReg(ArgGPRs);
asb wrote:
> xiangzhai wrote:
> > `RegIdx % 2 == 1` is an odd register, not an even, but the comment is "ensure it is assigned to an even register".
> The comment and code are correct. If we would use an odd register, we 'waste' it by mark it as allocated to ensure that an even register will be used. I'll add an extra comment to make it a bit clearer - thanks for the feedback.
Thanks for your teaching!


More information about the llvm-commits mailing list