[llvm] r321810 - [X86] Add common CHECK prefix for tests without SSE/AVX codegen
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 10:23:46 PST 2018
Author: rksimon
Date: Thu Jan 4 10:23:46 2018
New Revision: 321810
URL: http://llvm.org/viewvc/llvm-project?rev=321810&view=rev
Log:
[X86] Add common CHECK prefix for tests without SSE/AVX codegen
Modified:
llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/combine-udiv.ll
llvm/trunk/test/CodeGen/X86/combine-urem.ll
Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=321810&r1=321809&r2=321810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Thu Jan 4 10:23:46 2018
@@ -1,43 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (sdiv undef, x) -> 0
define <4 x i32> @combine_vec_sdiv_undef0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_sdiv_undef0:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_sdiv_undef0:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_sdiv_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = sdiv <4 x i32> undef, %x
ret <4 x i32> %1
}
; fold (sdiv x, undef) -> undef
define <4 x i32> @combine_vec_sdiv_undef1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_sdiv_undef1:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_sdiv_undef1:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_sdiv_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = sdiv <4 x i32> %x, undef
ret <4 x i32> %1
}
; fold (sdiv x, 1) -> x
define <4 x i32> @combine_vec_sdiv_by_one(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_sdiv_by_one:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_sdiv_by_one:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_sdiv_by_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = sdiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %1
}
@@ -62,19 +50,12 @@ define <4 x i32> @combine_vec_sdiv_by_ne
; TODO fold (sdiv x, x) -> 1
define i32 @combine_sdiv_dupe(i32 %x) {
-; SSE-LABEL: combine_sdiv_dupe:
-; SSE: # %bb.0:
-; SSE-NEXT: movl %edi, %eax
-; SSE-NEXT: cltd
-; SSE-NEXT: idivl %edi
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_sdiv_dupe:
-; AVX: # %bb.0:
-; AVX-NEXT: movl %edi, %eax
-; AVX-NEXT: cltd
-; AVX-NEXT: idivl %edi
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_sdiv_dupe:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %edi
+; CHECK-NEXT: retq
%1 = sdiv i32 %x, %x
ret i32 %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=321810&r1=321809&r2=321810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Thu Jan 4 10:23:46 2018
@@ -1,51 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (srem undef, x) -> 0
define <4 x i32> @combine_vec_srem_undef0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_undef0:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_srem_undef0:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_srem_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = srem <4 x i32> undef, %x
ret <4 x i32> %1
}
; fold (srem x, undef) -> undef
define <4 x i32> @combine_vec_srem_undef1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_undef1:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_srem_undef1:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_srem_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = srem <4 x i32> %x, undef
ret <4 x i32> %1
}
; TODO fold (srem x, x) -> 0
define i32 @combine_srem_dupe(i32 %x) {
-; SSE-LABEL: combine_srem_dupe:
-; SSE: # %bb.0:
-; SSE-NEXT: movl %edi, %eax
-; SSE-NEXT: cltd
-; SSE-NEXT: idivl %edi
-; SSE-NEXT: movl %edx, %eax
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_srem_dupe:
-; AVX: # %bb.0:
-; AVX-NEXT: movl %edi, %eax
-; AVX-NEXT: cltd
-; AVX-NEXT: idivl %edi
-; AVX-NEXT: movl %edx, %eax
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_srem_dupe:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cltd
+; CHECK-NEXT: idivl %edi
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: retq
%1 = srem i32 %x, %x
ret i32 %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-udiv.ll?rev=321810&r1=321809&r2=321810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-udiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-udiv.ll Thu Jan 4 10:23:46 2018
@@ -1,49 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (udiv undef, x) -> 0
define <4 x i32> @combine_vec_udiv_undef0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_udiv_undef0:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_udiv_undef0:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_udiv_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = udiv <4 x i32> undef, %x
ret <4 x i32> %1
}
; fold (udiv x, undef) -> undef
define <4 x i32> @combine_vec_udiv_undef1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_udiv_undef1:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_udiv_undef1:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_udiv_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = udiv <4 x i32> %x, undef
ret <4 x i32> %1
}
; TODO fold (udiv x, x) -> 1
define i32 @combine_udiv_dupe(i32 %x) {
-; SSE-LABEL: combine_udiv_dupe:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: movl %edi, %eax
-; SSE-NEXT: divl %edi
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_udiv_dupe:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: movl %edi, %eax
-; AVX-NEXT: divl %edi
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_udiv_dupe:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: divl %edi
+; CHECK-NEXT: retq
%1 = udiv i32 %x, %x
ret i32 %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-urem.ll?rev=321810&r1=321809&r2=321810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-urem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-urem.ll Thu Jan 4 10:23:46 2018
@@ -1,51 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (urem undef, x) -> 0
define <4 x i32> @combine_vec_urem_undef0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_urem_undef0:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_urem_undef0:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_urem_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = urem <4 x i32> undef, %x
ret <4 x i32> %1
}
; fold (urem x, undef) -> undef
define <4 x i32> @combine_vec_urem_undef1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_urem_undef1:
-; SSE: # %bb.0:
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_vec_urem_undef1:
-; AVX: # %bb.0:
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_vec_urem_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
%1 = urem <4 x i32> %x, undef
ret <4 x i32> %1
}
; TODO fold (urem x, x) -> 0
define i32 @combine_urem_dupe(i32 %x) {
-; SSE-LABEL: combine_urem_dupe:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: movl %edi, %eax
-; SSE-NEXT: divl %edi
-; SSE-NEXT: movl %edx, %eax
-; SSE-NEXT: retq
-;
-; AVX-LABEL: combine_urem_dupe:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: movl %edi, %eax
-; AVX-NEXT: divl %edi
-; AVX-NEXT: movl %edx, %eax
-; AVX-NEXT: retq
+; CHECK-LABEL: combine_urem_dupe:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: divl %edi
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: retq
%1 = urem i32 %x, %x
ret i32 %1
}
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