[llvm] r321807 - [X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 10:20:46 PST 2018
Author: rksimon
Date: Thu Jan 4 10:20:46 2018
New Revision: 321807
URL: http://llvm.org/viewvc/llvm-project?rev=321807&view=rev
Log:
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM
Modified:
llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/combine-udiv.ll
llvm/trunk/test/CodeGen/X86/combine-urem.ll
Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=321807&r1=321806&r2=321807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Thu Jan 4 10:20:46 2018
@@ -60,6 +60,80 @@ define <4 x i32> @combine_vec_sdiv_by_ne
ret <4 x i32> %1
}
+; TODO fold (sdiv x, x) -> 1
+define i32 @combine_sdiv_dupe(i32 %x) {
+; SSE-LABEL: combine_sdiv_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %edi
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_sdiv_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %edi
+; AVX-NEXT: retq
+ %1 = sdiv i32 %x, %x
+ ret i32 %1
+}
+
+define <4 x i32> @combine_vec_sdiv_dupe(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_sdiv_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: pextrd $1, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: movl %eax, %ecx
+; SSE-NEXT: movd %xmm0, %esi
+; SSE-NEXT: movl %esi, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %esi
+; SSE-NEXT: movd %eax, %xmm1
+; SSE-NEXT: pinsrd $1, %ecx, %xmm1
+; SSE-NEXT: pextrd $2, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: pinsrd $2, %eax, %xmm1
+; SSE-NEXT: pextrd $3, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: pinsrd $3, %eax, %xmm1
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_vec_sdiv_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: vpextrd $1, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: movl %eax, %ecx
+; AVX-NEXT: vmovd %xmm0, %esi
+; AVX-NEXT: movl %esi, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %esi
+; AVX-NEXT: vmovd %eax, %xmm1
+; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $2, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $3, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %1 = sdiv <4 x i32> %x, %x
+ ret <4 x i32> %1
+}
+
; fold (sdiv x, y) -> (udiv x, y) iff x and y are positive
define <4 x i32> @combine_vec_sdiv_by_pos0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_sdiv_by_pos0:
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=321807&r1=321806&r2=321807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Thu Jan 4 10:20:46 2018
@@ -29,6 +29,82 @@ define <4 x i32> @combine_vec_srem_undef
ret <4 x i32> %1
}
+; TODO fold (srem x, x) -> 0
+define i32 @combine_srem_dupe(i32 %x) {
+; SSE-LABEL: combine_srem_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %edi
+; SSE-NEXT: movl %edx, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_srem_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %edi
+; AVX-NEXT: movl %edx, %eax
+; AVX-NEXT: retq
+ %1 = srem i32 %x, %x
+ ret i32 %1
+}
+
+define <4 x i32> @combine_vec_srem_dupe(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_srem_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: pextrd $1, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: movl %edx, %ecx
+; SSE-NEXT: movd %xmm0, %esi
+; SSE-NEXT: movl %esi, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %esi
+; SSE-NEXT: movd %edx, %xmm1
+; SSE-NEXT: pinsrd $1, %ecx, %xmm1
+; SSE-NEXT: pextrd $2, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: pinsrd $2, %edx, %xmm1
+; SSE-NEXT: pextrd $3, %xmm0, %ecx
+; SSE-NEXT: movl %ecx, %eax
+; SSE-NEXT: cltd
+; SSE-NEXT: idivl %ecx
+; SSE-NEXT: pinsrd $3, %edx, %xmm1
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_vec_srem_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: vpextrd $1, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: movl %edx, %ecx
+; AVX-NEXT: vmovd %xmm0, %esi
+; AVX-NEXT: movl %esi, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %esi
+; AVX-NEXT: vmovd %edx, %xmm1
+; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $2, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $3, %xmm0, %ecx
+; AVX-NEXT: movl %ecx, %eax
+; AVX-NEXT: cltd
+; AVX-NEXT: idivl %ecx
+; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %1 = srem <4 x i32> %x, %x
+ ret <4 x i32> %1
+}
+
; fold (srem x, y) -> (urem x, y) iff x and y are positive
define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_srem_by_pos0:
Modified: llvm/trunk/test/CodeGen/X86/combine-udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-udiv.ll?rev=321807&r1=321806&r2=321807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-udiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-udiv.ll Thu Jan 4 10:20:46 2018
@@ -29,6 +29,72 @@ define <4 x i32> @combine_vec_udiv_undef
ret <4 x i32> %1
}
+; TODO fold (udiv x, x) -> 1
+define i32 @combine_udiv_dupe(i32 %x) {
+; SSE-LABEL: combine_udiv_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: divl %edi
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_udiv_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: divl %edi
+; AVX-NEXT: retq
+ %1 = udiv i32 %x, %x
+ ret i32 %1
+}
+
+define <4 x i32> @combine_vec_udiv_dupe(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_udiv_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: pextrd $1, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: movl %eax, %ecx
+; SSE-NEXT: movd %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: movd %eax, %xmm1
+; SSE-NEXT: pinsrd $1, %ecx, %xmm1
+; SSE-NEXT: pextrd $2, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: pinsrd $2, %eax, %xmm1
+; SSE-NEXT: pextrd $3, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: pinsrd $3, %eax, %xmm1
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_vec_udiv_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: vpextrd $1, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: movl %eax, %ecx
+; AVX-NEXT: vmovd %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vmovd %eax, %xmm1
+; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $2, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $3, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %1 = udiv <4 x i32> %x, %x
+ ret <4 x i32> %1
+}
+
; fold (udiv x, (1 << c)) -> x >>u c
define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_pow2a:
Modified: llvm/trunk/test/CodeGen/X86/combine-urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-urem.ll?rev=321807&r1=321806&r2=321807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-urem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-urem.ll Thu Jan 4 10:20:46 2018
@@ -29,6 +29,74 @@ define <4 x i32> @combine_vec_urem_undef
ret <4 x i32> %1
}
+; TODO fold (urem x, x) -> 0
+define i32 @combine_urem_dupe(i32 %x) {
+; SSE-LABEL: combine_urem_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: divl %edi
+; SSE-NEXT: movl %edx, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_urem_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: divl %edi
+; AVX-NEXT: movl %edx, %eax
+; AVX-NEXT: retq
+ %1 = urem i32 %x, %x
+ ret i32 %1
+}
+
+define <4 x i32> @combine_vec_urem_dupe(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_urem_dupe:
+; SSE: # %bb.0:
+; SSE-NEXT: pextrd $1, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: movl %edx, %ecx
+; SSE-NEXT: movd %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: movd %edx, %xmm1
+; SSE-NEXT: pinsrd $1, %ecx, %xmm1
+; SSE-NEXT: pextrd $2, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: pinsrd $2, %edx, %xmm1
+; SSE-NEXT: pextrd $3, %xmm0, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: divl %eax
+; SSE-NEXT: pinsrd $3, %edx, %xmm1
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_vec_urem_dupe:
+; AVX: # %bb.0:
+; AVX-NEXT: vpextrd $1, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: movl %edx, %ecx
+; AVX-NEXT: vmovd %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vmovd %edx, %xmm1
+; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $2, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
+; AVX-NEXT: vpextrd $3, %xmm0, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: divl %eax
+; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %1 = urem <4 x i32> %x, %x
+ ret <4 x i32> %1
+}
+
; fold (urem x, pow2) -> (and x, (pow2-1))
define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_urem_by_pow2a:
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