[PATCH] D41185: [ARM] Fix endianness of Thumb .inst.w directive
Oliver Stannard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 02:08:43 PST 2018
olista01 added a comment.
This is described in the "Instruction endianness" section in the architecture reference manual, which is section A3.3.1 in the latest version of the v7-A/R manual. Here's the relevant bit:
A3.3.1 Instruction endianness
In ARMv7-A, the mapping of instruction memory is always little-endian. In ARMv7-R, instruction endianness can
be controlled at the system level, see Instruction endianness static configuration, ARMv7-R only on page A3-112.
Note: For information about data memory endianness control, see Endianness mapping register, ENDIANSTATE on
Before ARMv7, the ARM architecture included legacy support for an alternative big-endian memory model,
described as BE-32 and controlled by SCTLR.B bit, bit of the register, see Endian configuration and control on
page AppxL-2516. ARMv7 does not support BE-32 operation, and bit SCTLR is RAZ/SBZP.
Where legacy object code for ARM processors contains instructions with a big-endian byte order, the removal of
support for BE-32 operation requires the instructions in the object files to have their bytes reversed for the code to
be executed on an ARMv7 processor. This means that:
- each Thumb instruction, whether a 32-bit Thumb instruction or a 16-bit Thumb instruction, must have the
byte order of each halfword of instruction reversed
- each ARM instruction must have the byte order of each word of instruction reversed.
For most situations, this can be handled in the link stage of a tool-flow, provided the object files include sufficient
information to permit this to happen. In practice, this is the situation for all applications with the ARMv7-A profile.
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