[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Javed Absar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 2 02:23:41 PST 2018
javed.absar added inline comments.
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:771
+ let Size = 16;
Looks like some code duplication between PPR and PPR_3b could be factored out by creating an intermediate class. You may want to consider it.
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