[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:771
+  let Size = 16;
+}
+
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Looks like some code duplication between PPR and PPR_3b could be factored out by creating an intermediate class. You may want to consider it.


https://reviews.llvm.org/D41441