[PATCH] D41653: [RISCV] Initial porting GlobalISel

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai created this revision.
xiangzhai added a reviewer: asb.
Herald added subscribers: sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar, kristof.beyls, rovka, mgorny.

Hi LLVM developers,

Motivation:

I am learning and practicing Instruction Selection <https://www.leetcode.cn/2017/12/porting-globalisel.html> by porting GlobalISel to RISCV target.

Status:

- Pass a dummy `CCAssignFn` to the `ValueHandler` constructor and override `ValueHandler::assignArg`, and it is better to refactory the existing `CC_RISCV32` function to conform to the `CCAssignFn` type in the next patch.
- RegisterBank supports 32bit and 64bit for FPR , but it only supports 32bit for General Purpose Register, because GPR64 had been merged into GPR in https://reviews.llvm.org/rL316159 and GlobalISel needs to consider about how to support variable-sized register classes concept implemented in https://reviews.llvm.org/D24631.
- Legalizer and InstructionSelector only cover some instructions, so if run testcase, for example, `calling-conv.ll`, it will throw such errors:

  LLVM ERROR: unable to legalize instruction: %1:_(s128) = G_SITOFP %0:_(s64); (in function: caller_mixed_scalar_libcalls)

It is an initial porting, so it is just able to run very simple testcase:

  $ cat return.ll
  
  define void @f0() {
    ret void
  }
  
  define i32 @f1() {
    ret i32 0
  }
  
  define i32 @f2() {
    %1 = call i32 @f1()
    ret i32 %1
  }
  
  $ llc -global-isel -march=riscv32 return.ll -o return-riscv32-global-isel.s
  
  f:
  	addi	sp, sp, -16
  	sw	ra, 12(sp)
  	sw	s0, 8(sp)
  	addi	s0, sp, 16
  	lw	s0, 8(sp)
  	lw	ra, 12(sp)
  	addi	sp, sp, 16
  	ret
  
  f1:
  	addi	sp, sp, -16
  	sw	ra, 12(sp)
  	sw	s0, 8(sp)
  	addi	s0, sp, 16
  	lw	s0, 8(sp)
  	lw	ra, 12(sp)
  	addi	sp, sp, 16
  	ret
  
  f2:
  	addi	sp, sp, -16
  	sw	ra, 12(sp)
  	sw	s0, 8(sp)
  	addi	s0, sp, 16
  	jalr	ra, f1, 0
  	lw	s0, 8(sp)
  	lw	ra, 12(sp)
  	addi	sp, sp, 16
  	ret

Please review my patch, and give me some suggestion, thanks for your teaching!

Regards,
Leslie Zhai


Repository:
  rL LLVM

https://reviews.llvm.org/D41653

Files:
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/LLVMBuild.txt
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVCallLowering.cpp
  lib/Target/RISCV/RISCVCallLowering.h
  lib/Target/RISCV/RISCVInstructionSelector.cpp
  lib/Target/RISCV/RISCVLegalizerInfo.cpp
  lib/Target/RISCV/RISCVLegalizerInfo.h
  lib/Target/RISCV/RISCVRegisterBankInfo.cpp
  lib/Target/RISCV/RISCVRegisterBankInfo.h
  lib/Target/RISCV/RISCVRegisterBanks.td
  lib/Target/RISCV/RISCVSubtarget.cpp
  lib/Target/RISCV/RISCVSubtarget.h
  lib/Target/RISCV/RISCVTargetMachine.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41653.128381.patch
Type: text/x-patch
Size: 63091 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180101/2dd85520/attachment.bin>