[PATCH] D41560: [X86] Make v2i1 and v4i1 legal types without VLX

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 128378.
craig.topper added a comment.

Fixes to not sign extend condition of selects without VLX. Use 512-bit selects instead.


https://reviews.llvm.org/D41560

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrVecCompiler.td
  test/Analysis/CostModel/X86/cast.ll
  test/CodeGen/X86/avx512-calling-conv.ll
  test/CodeGen/X86/avx512-cvt.ll
  test/CodeGen/X86/avx512-ext.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512-mask-op.ll
  test/CodeGen/X86/avx512-vec-cmp.ll
  test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512vl-vec-cmp.ll
  test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
  test/CodeGen/X86/compress_expand.ll
  test/CodeGen/X86/masked_gather_scatter.ll
  test/CodeGen/X86/masked_memop.ll
  test/CodeGen/X86/pr33349.ll
  test/CodeGen/X86/sse-fsignum.ll
  test/CodeGen/X86/vector-shuffle-v1.ll
  test/CodeGen/X86/vselect-pcmp.ll