[llvm] r321610 - [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 31 10:59:30 PST 2017
Author: rksimon
Date: Sun Dec 31 10:59:30 2017
New Revision: 321610
URL: http://llvm.org/viewvc/llvm-project?rev=321610&view=rev
Log:
[X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
As it has a scalar source we don't treat it as a target shuffle so needs special handling.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/vector-pcmp.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=321610&r1=321609&r2=321610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Dec 31 10:59:30 2017
@@ -30923,6 +30923,11 @@ static SDValue combineExtractWithShuffle
if (SrcSVT == MVT::i1 || !isa<ConstantSDNode>(Idx))
return SDValue();
+ // Handle extract(broadcast(scalar_value)), it doesn't matter what index is.
+ if (X86ISD::VBROADCAST == Src.getOpcode() &&
+ Src.getOperand(0).getValueType() == VT)
+ return Src.getOperand(0);
+
// Resolve the target shuffle inputs and mask.
SmallVector<int, 16> Mask;
SmallVector<SDValue, 2> Ops;
Modified: llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll?rev=321610&r1=321609&r2=321610&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll Sun Dec 31 10:59:30 2017
@@ -874,39 +874,33 @@ define float @broadcast_lifetime() nounw
; X32-LABEL: broadcast_lifetime:
; X32: ## %bb.0:
; X32-NEXT: pushl %esi
-; X32-NEXT: subl $56, %esp
+; X32-NEXT: subl $40, %esp
; X32-NEXT: leal {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl %esi, (%esp)
; X32-NEXT: calll _gfunc
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ## 16-byte Spill
+; X32-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## 4-byte Spill
; X32-NEXT: movl %esi, (%esp)
; X32-NEXT: calll _gfunc
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: vpermilps $0, {{[0-9]+}}(%esp), %xmm1 ## 16-byte Folded Reload
-; X32-NEXT: ## xmm1 = mem[0,0,0,0]
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X32-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; X32-NEXT: vsubss {{[0-9]+}}(%esp), %xmm0, %xmm0 ## 4-byte Folded Reload
; X32-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: flds {{[0-9]+}}(%esp)
-; X32-NEXT: addl $56, %esp
+; X32-NEXT: addl $40, %esp
; X32-NEXT: popl %esi
; X32-NEXT: retl
;
; X64-LABEL: broadcast_lifetime:
; X64: ## %bb.0:
; X64-NEXT: subq $40, %rsp
-; X64-NEXT: movq %rsp, %rdi
+; X64-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; X64-NEXT: callq _gfunc
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ## 16-byte Spill
-; X64-NEXT: movq %rsp, %rdi
+; X64-NEXT: vmovss %xmm0, {{[0-9]+}}(%rsp) ## 4-byte Spill
+; X64-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; X64-NEXT: callq _gfunc
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: vpermilps $0, {{[0-9]+}}(%rsp), %xmm1 ## 16-byte Folded Reload
-; X64-NEXT: ## xmm1 = mem[0,0,0,0]
-; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; X64-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; X64-NEXT: vsubss {{[0-9]+}}(%rsp), %xmm0, %xmm0 ## 4-byte Folded Reload
; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq
%1 = alloca <4 x float>, align 16
Modified: llvm/trunk/test/CodeGen/X86/vector-pcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-pcmp.ll?rev=321610&r1=321609&r2=321610&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-pcmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-pcmp.ll Sun Dec 31 10:59:30 2017
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; Lower common integer comparisons such as 'isPositive' efficiently:
; https://llvm.org/bugs/show_bug.cgi?id=26701
@@ -84,31 +84,13 @@ define <2 x i64> @test_pcmpgtq(<2 x i64>
}
define <1 x i128> @test_strange_type(<1 x i128> %x) {
-; SSE-LABEL: test_strange_type:
-; SSE: # %bb.0:
-; SSE-NEXT: sarq $63, %rsi
-; SSE-NEXT: notq %rsi
-; SSE-NEXT: movq %rsi, %rax
-; SSE-NEXT: movq %rsi, %rdx
-; SSE-NEXT: retq
-;
-; AVX1-LABEL: test_strange_type:
-; AVX1: # %bb.0:
-; AVX1-NEXT: sarq $63, %rsi
-; AVX1-NEXT: notq %rsi
-; AVX1-NEXT: movq %rsi, %rax
-; AVX1-NEXT: movq %rsi, %rdx
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: test_strange_type:
-; AVX2: # %bb.0:
-; AVX2-NEXT: sarq $63, %rsi
-; AVX2-NEXT: notq %rsi
-; AVX2-NEXT: vmovq %rsi, %xmm0
-; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
-; AVX2-NEXT: vmovq %xmm0, %rax
-; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
-; AVX2-NEXT: retq
+; CHECK-LABEL: test_strange_type:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sarq $63, %rsi
+; CHECK-NEXT: notq %rsi
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: movq %rsi, %rdx
+; CHECK-NEXT: retq
%sign = ashr <1 x i128> %x, <i128 127>
%not = xor <1 x i128> %sign, <i128 -1>
ret <1 x i128> %not
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