[llvm] r321464 - [DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Dec 26 15:27:44 2017
New Revision: 321464

URL: http://llvm.org/viewvc/llvm-project?rev=321464&view=rev
Log:
[DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue

Reduced from oss-fuzz #4782 test case

Added:
    llvm/trunk/test/CodeGen/AArch64/combine-and-like.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=321464&r1=321463&r2=321464&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 26 15:27:44 2017
@@ -3642,15 +3642,18 @@ SDValue DAGCombiner::visitANDLike(SDValu
   if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
       VT.getSizeInBits() <= 64) {
     if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
-      APInt ADDC = ADDI->getAPIntValue();
-      if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
+      if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
         // immediate for an add, but it is legal if its top c2 bits are set,
         // transform the ADD so the immediate doesn't need to be materialized
         // in a register.
-        if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+        APInt ADDC = ADDI->getAPIntValue();
+        APInt SRLC = SRLI->getAPIntValue();
+        if (ADDC.getMinSignedBits() <= 64 &&
+            SRLC.ult(VT.getSizeInBits()) &&
+            !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
           APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
-                                             SRLI->getZExtValue());
+                                             SRLC.getZExtValue());
           if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
             ADDC |= Mask;
             if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {

Added: llvm/trunk/test/CodeGen/AArch64/combine-and-like.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/combine-and-like.ll?rev=321464&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/combine-and-like.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/combine-and-like.ll Tue Dec 26 15:27:44 2017
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+define i32 @f(i32 %a0) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ret
+  %1 = lshr i32 %a0, 2147483647
+  %2 = add i32 %1, 2147483647
+  %3 = and i32 %2, %1
+  ret i32 %3
+}