[PATCH] D41587: [AArch64] Change order of candidate FMLS patterns

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso created this revision.
mssimpso added reviewers: fhahn, evandro, mcrosier.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

A few floating-point SPEC benchmarks are regressed on Falkor after https://reviews.llvm.org/rL319980. That patch added new patterns to the machine combiner for transforming (fsub (fmul x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source operand is an fmul are transformed. We previously only matched the case where the second source operand of an fsub was an fmul, transforming (fsub z (fmul x y)) into (fmls z x y). Now, if we have an fsub where both source operands are fmuls, both of the above patterns are applicable.

However, the order in which we add the patterns to the list of candidates determines the transformation that takes place, since only the first pattern that matches will be used. This patch changes the order these two patterns are added to the list of candidates such that we prefer the case where the second source operand is an fmul (the fmls case), rather than the other one (the fmla/fneg case). When both source operands are fmuls, this ordering results in fewer instructions. Please refer to the added test cases for examples.


https://reviews.llvm.org/D41587

Files:
  lib/Target/AArch64/AArch64InstrInfo.cpp
  test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir

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