[PATCH] D41341: [X86] WIP disable 512-bit vectors during type legalization for prefer-vector-width

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 128053.
craig.topper added a comment.
Herald added a subscriber: mgorny.

This patch now contains fixes for all of the known issues with lowering trying to use 512-bit types for extending to make operations legal.

I've modified the logic for disable 512-bit types a little. I now only disable 512-bit types if the ABI doesn't require them, the CPU prefers 256-bit, and we have the AVX512VL(the feature that enables masking on 128/256-bit registers) instruction set. This is fine for SKX, but means -mprefer-vector-width=256 will not disable the use of 512-bit regs on KNL as it doesn't have AVX512VL. But KNL doesn't have the frequency issue either so its probably ok. This was mainly done to avoid having to deal with a situatiion where we would support masking on scalar operations, but not being able to doing any masking on vectors. By introducing the VLX requirements before disabling 512-bit vectors we are able support ensure we always have vector+scalar masking and we can continue widening to 512-bits for masking when AVX512VL isn't available.

I've added an experimental pass just befoer isel that detects intrinsics and ABI requirements for needing 512-bit vectors and adds the appropriate require-vector-width attribute based on what it finds. This should hopefully avoid any miscompiles or isel failures for testing this feature. It currently only sets the required width to 256 or 512, but it can be made more generic in the future.

I found all of the lowering fixes by enabling the pass and forcing the prefer-vector-width-256 feature on for all CPUs. Then looking for assertion failures and llvm_unreahables on the X86 codegen lit tests.

I plan to add more directed tests for each of the lowering fixes.


https://reviews.llvm.org/D41341

Files:
  lib/Target/X86/CMakeLists.txt
  lib/Target/X86/X86.h
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  lib/Target/X86/X86TargetMachine.cpp
  lib/Target/X86/X86TargetTransformInfo.cpp
  lib/Target/X86/X86VectorWidthInfer.cpp
  test/CodeGen/X86/prefer-avx256-shift.ll
  test/CodeGen/X86/prefer-avx256-wide-mul.ll
  test/Transforms/LoopVectorize/X86/avx512.ll

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