[llvm] r321367 - [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32

[Dmitry Preobrazhensky via llvm-commits]

Author: dpreobra
Date: Fri Dec 22 09:13:28 2017
New Revision: 321367

URL: http://llvm.org/viewvc/llvm-project?rev=321367&view=rev
Log:
[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32

See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41186

Modified:
    llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    llvm/trunk/test/MC/AMDGPU/ds.s
    llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=321367&r1=321366&r2=321367&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Fri Dec 22 09:13:28 2017
@@ -3852,7 +3852,9 @@ AMDGPUAsmParser::parseSwizzleOp(OperandV
 
     return Ok? MatchOperand_Success : MatchOperand_ParseFail;
   } else {
-    return MatchOperand_NoMatch;
+    // Swizzle "offset" operand is optional.
+    // If it is omitted, try parsing other optional operands.
+    return parseOptionalOperand(Operands);
   }
 }
 

Modified: llvm/trunk/test/MC/AMDGPU/ds.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds.s?rev=321367&r1=321366&r2=321367&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds.s Fri Dec 22 09:13:28 2017
@@ -511,6 +511,10 @@ ds_swizzle_b32 v8, v2
 // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 
+ds_swizzle_b32 v8, v2 gds
+// SICI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0xd6,0xd8,0x02,0x00,0x00,0x08]
+// VI:   ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
+
 ds_swizzle_b32 v8, v2 offset:0xFFFF
 // SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08]

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt?rev=321367&r1=321366&r2=321367&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt Fri Dec 22 09:13:28 2017
@@ -171,6 +171,9 @@
 # VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
 
+# VI:   ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
+0x00 0x00 0x7b 0xd8 0x02 0x00 0x00 0x08
+
 # VI:   ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08