[llvm] r321356 - [ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 22 05:05:52 PST 2017
Author: rovka
Date: Fri Dec 22 05:05:51 2017
New Revision: 321356
URL: http://llvm.org/viewvc/llvm-project?rev=321356&view=rev
Log:
[ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32
Mark conversions between pointers and 32-bit scalars as legal, map them
to the GPR and select to a simple COPY.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Fri Dec 22 05:05:51 2017
@@ -788,6 +788,28 @@ bool ARMInstructionSelector::select(Mach
I.setDesc(TII.get(COPY));
return selectCopy(I, TII, MRI, TRI, RBI);
}
+ case G_INTTOPTR:
+ case G_PTRTOINT: {
+ auto SrcReg = I.getOperand(1).getReg();
+ auto DstReg = I.getOperand(0).getReg();
+
+ const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
+ const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
+
+ if (SrcRegBank.getID() != DstRegBank.getID()) {
+ DEBUG(dbgs()
+ << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
+ return false;
+ }
+
+ if (SrcRegBank.getID() != ARM::GPRRegBankID) {
+ DEBUG(dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
+ return false;
+ }
+
+ I.setDesc(TII.get(COPY));
+ return selectCopy(I, TII, MRI, TRI, RBI);
+ }
case G_SELECT:
return selectSelect(MIB, MRI);
case G_ICMP: {
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Fri Dec 22 05:05:51 2017
@@ -126,6 +126,12 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({Op, s32}, Legal);
}
+ setAction({G_INTTOPTR, p0}, Legal);
+ setAction({G_INTTOPTR, 1, s32}, Legal);
+
+ setAction({G_PTRTOINT, s32}, Legal);
+ setAction({G_PTRTOINT, 1, p0}, Legal);
+
for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
setAction({Op, s32}, Legal);
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Fri Dec 22 05:05:51 2017
@@ -227,6 +227,8 @@ ARMRegisterBankInfo::getInstrMapping(con
case G_ZEXT:
case G_ANYEXT:
case G_GEP:
+ case G_INTTOPTR:
+ case G_PTRTOINT:
// FIXME: We're abusing the fact that everything lives in a GPR for now; in
// the real world we would use different mappings.
OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Fri Dec 22 05:05:51 2017
@@ -49,6 +49,9 @@
define void @test_constant_cimm() { ret void }
define void @test_pointer_constant() { ret void }
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
+
define void @test_select_s32() { ret void }
define void @test_select_ptr() { ret void }
@@ -1124,6 +1127,54 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY [[INT]]
+
+ %r0 = COPY %1(p0)
+ ; CHECK: %r0 = COPY [[PTR]]
+
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY [[PTR]]
+
+ %r0 = COPY %1(s32)
+ ; CHECK: %r0 = COPY [[INT]]
+
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: true
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Fri Dec 22 05:05:51 2017
@@ -3,6 +3,9 @@
define void @test_sext_s8() { ret void }
define void @test_zext_s16() { ret void }
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
+
define void @test_add_s8() { ret void }
define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
@@ -101,6 +104,50 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ ; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}:_(p0) = G_INTTOPTR {{%[0-9]+}}
+ %r0 = COPY %1(p0)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ ; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}:_(s32) = G_PTRTOINT {{%[0-9]+}}
+ %r0 = COPY %1(s32)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized: false
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=321356&r1=321355&r2=321356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Fri Dec 22 05:05:51 2017
@@ -24,6 +24,9 @@
define void @test_constants() { ret void }
+ define void @test_inttoptr_s32() { ret void }
+ define void @test_ptrtoint_s32() { ret void }
+
@a_global = global float 1.0
define void @test_globals() { ret void }
@@ -497,6 +500,44 @@ body: |
BX_RET 14, %noreg, implicit %r0
...
---
+name: test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ %0(s32) = COPY %r0
+ %1(p0) = G_INTTOPTR %0(s32)
+ %r0 = COPY %1(p0)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ %0(p0) = COPY %r0
+ %1(s32) = G_PTRTOINT %0(p0)
+ %r0 = COPY %1(s32)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
name: test_globals
# CHECK-LABEL: name: test_globals
legalized: true
More information about the llvm-commits
mailing list