[llvm] r321278 - [X86] Add (or (and X, c1), c2) -> (and (or X, c2), c1|c2) non-splat vector test

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Dec 21 08:08:41 2017
New Revision: 321278

URL: http://llvm.org/viewvc/llvm-project?rev=321278&view=rev
Log:
[X86] Add (or (and X, c1), c2) -> (and (or X, c2), c1|c2) non-splat vector test

Modified:
    llvm/trunk/test/CodeGen/X86/combine-or.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-or.ll?rev=321278&r1=321277&r2=321278&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-or.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-or.ll Thu Dec 21 08:08:41 2017
@@ -430,8 +430,7 @@ define <4 x i32> @test2f(<4 x i32> %a, <
   ret <4 x i32> %or
 }
 
-; TODO: Why would we do this?
-; (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
+; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0
 
 define <2 x i64> @or_and_v2i64(<2 x i64> %a0) {
 ; CHECK-LABEL: or_and_v2i64:
@@ -444,11 +443,22 @@ define <2 x i64> @or_and_v2i64(<2 x i64>
   ret <2 x i64> %2
 }
 
-; If all masked bits are going to be set, that's a constant fold.
-
 define <4 x i32> @or_and_v4i32(<4 x i32> %a0) {
 ; CHECK-LABEL: or_and_v4i32:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = and <4 x i32> %a0, <i32 1, i32 3, i32 5, i32 7>
+  %2 = or <4 x i32> %1, <i32 3, i32 2, i32 15, i32 2>
+  ret <4 x i32> %2
+}
+
+; If all masked bits are going to be set, that's a constant fold.
+
+define <4 x i32> @or_and_v4i32_fold(<4 x i32> %a0) {
+; CHECK-LABEL: or_and_v4i32_fold:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [3,3,3,3]
 ; CHECK-NEXT:    retq
   %1 = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>