[PATCH] D41411: [PowerPC] Fix parest build failure in SPEC2017.

[Tony Jiang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321276: [PowerPC] Fix parest build failure in SPEC2017. (authored by jtony, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41411?vs=127584&id=127886#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41411

Files:
  llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll


Index: llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
+++ llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
@@ -0,0 +1,15 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Ensure we don't crash by trying to convert directly from a subword load
+; to a ppc_fp128 as we do for conversions to f32/f64.
+define ppc_fp128 @test(i16* nocapture readonly %Ptr) {
+entry:
+  %0 = load i16, i16* %Ptr, align 2
+  %conv = uitofp i16 %0 to ppc_fp128
+  ret ppc_fp128 %conv
+; CHECK: lhz [[LD:[0-9]+]], 0(3)
+; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
+; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
+; CHECK: bl __gcc_qadd
+}
Index: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11882,6 +11882,12 @@
   SDLoc dl(N);
   SDValue Op(N, 0);
 
+  // Don't handle ppc_fp128 here or i1 conversions.
+  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
+    return SDValue();
+  if (Op.getOperand(0).getValueType() == MVT::i1)
+    return SDValue();
+
   SDValue FirstOperand(Op.getOperand(0));
   bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
     (FirstOperand.getValueType() == MVT::i8 ||
@@ -11910,11 +11916,6 @@
       return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld);
   }
 
-  // Don't handle ppc_fp128 here or i1 conversions.
-  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
-    return SDValue();
-  if (Op.getOperand(0).getValueType() == MVT::i1)
-    return SDValue();
 
   // For i32 intermediate values, unfortunately, the conversion functions
   // leave the upper 32 bits of the value are undefined. Within the set of


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