[PATCH] D41446: [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Thanks Sander, I left some comments.

This is needed for SVE, because some instructions force 2 registers to be equal for certain versions of the instruction. e.g.

  add z1, z2, z3 # OK
  add z1, p0/m, z2, z3 # Not OK, for predicated add the result reg must be equal to the first data src reg.

Adding Oliver as well, maybe you have some thoughts on the error handling in this case. Is there another way to handle this case?


https://reviews.llvm.org/D41446