[PATCH] D41440: [X86][SSE] Split large PAVGB/PAVGW vectors to legal widths

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

What happens with types that are multiple of 128 bits,



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:33862
   if (Subtarget.hasBWI()) {
-    if (VT.getSizeInBits() > 512)
+    if (VT.getSizeInBits() > 512 && (VT.getSizeInBits() % 512) != 0)
       return SDValue();
----------------
Isn't the modulo guaranteed true by the isPowerOf2_32(NumElems) check above? And if it wasn't it would mean we would do something different for a 384-bit vector with only SSE2(since its divisible by 128) than we would for AVX2(since its not divisible by 256)


Repository:
  rL LLVM

https://reviews.llvm.org/D41440