[PATCH] D41350: [DAGCombine] Improve ReduceLoadWidth for SRL
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 20 08:15:14 PST 2017
RKSimon added a comment.
x86 codegen looks OK, one minor but no other comments from me.
================
Comment at: test/CodeGen/X86/h-registers-1.ll:76
; GNUX32-NEXT: retq
+ i64 %e, i64 %f, i64 %g, i64 %h) {
%sa = lshr i64 %a, 8
----------------
For clarity please can you put this back on the previous line with the other arguments?
https://reviews.llvm.org/D41350
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