[llvm] r321177 - [Hexagon] Adjust the value type for BCvt in LowerFormalArguments

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Dec 20 06:44:05 2017
New Revision: 321177

URL: http://llvm.org/viewvc/llvm-project?rev=321177&view=rev
Log:
[Hexagon] Adjust the value type for BCvt in LowerFormalArguments

Added:
    llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=321177&r1=321176&r2=321177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Dec 20 06:44:05 2017
@@ -761,11 +761,13 @@ HexagonTargetLowering::LowerCall(TargetL
     // Promote the value if needed.
     switch (VA.getLocInfo()) {
       default:
-        // Loc info must be one of Full, SExt, ZExt, or AExt.
+        // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
         llvm_unreachable("Unknown loc info!");
-      case CCValAssign::BCvt:
       case CCValAssign::Full:
         break;
+      case CCValAssign::BCvt:
+        Arg = DAG.getBitcast(VA.getLocVT(), Arg);
+        break;
       case CCValAssign::SExt:
         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
         break;
@@ -1135,6 +1137,8 @@ SDValue HexagonTargetLowering::LowerForm
         unsigned VReg =
           RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
+        if (VA.getLocInfo() == CCValAssign::BCvt)
+          RegVT = VA.getValVT();
         SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
         // Treat values of type MVT::i1 specially: they are passed in
         // registers of type i32, but they need to remain as values of
@@ -1155,6 +1159,8 @@ SDValue HexagonTargetLowering::LowerForm
         unsigned VReg =
           RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
+        if (VA.getLocInfo() == CCValAssign::BCvt)
+          RegVT = VA.getValVT();
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
 
       // Single Vector

Added: llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll?rev=321177&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll Wed Dec 20 06:44:05 2017
@@ -0,0 +1,14 @@
+; RUN: llc -march=hexagon -debug-only=isel < %s 2>/dev/null
+; REQUIRES: asserts
+
+; Make sure that this doesn't crash. Debug option enabled a failing assertion
+; about type mismatch in formal arguments.
+; CHECK: vaddub
+
+define i1 @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = add <4 x i8> %a, %b
+        %1 = bitcast <4 x i8> %0 to <32 x i1>
+        %2 = extractelement <32 x i1> %1, i32 0
+	ret i1 %2
+}