[PATCH] D41445: [AArch64][AsmParser] Add isScalarReg() and repurpose isReg()

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: rengolin, mcrosier, evandro, fhahn, echristo.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead.

Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.


https://reviews.llvm.org/D41445

Files:
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

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