[PATCH] D41430: [ARM] Armv8-R DFB instruction

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/ARM/ARMInstrInfo.td:4813
+                "dfb", "", []>,
+                Requires<[IsARM, HasDFB]> , Sched<[WriteALU]> {
+                let Inst{31-0} = 0xf57ff04c;
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fhahn wrote:
> samparker wrote:
> > fhahn wrote:
> > > Are you sure about `Sched<[WriteALU]>`? It's an alias to the `DSB` instruction , which does not have a similar `Sched`
> > I'm not, but couldn't find where/how DSB got its scheduling info. Do you know where its defined? I should probably also add an InstAlias to DSB...
> The instruction is marked as having (unmodelled) side effects. That should tell the scheduler to not move instructions past this instruction, so I think there is no need to add scheduling info.
As this is memory relate WriteLd may be a better option (and probably more realistic in terms of timing generally). 


https://reviews.llvm.org/D41430