[PATCH] D41341: [X86] WIP disable 512-bit vectors during type legalization for prefer-vector-width

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added a comment.

> I looked into trying to add a 512-bit register feature that could be disabled instead like https://reviews.llvm.org/D41096 proposed, but I couldn't find a good way to make the existing command line options work. The tablegen generated subtarget feature system just doesn't allow for a wrapper/alias feature that implies other features.

Thanks for experimenting.



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Comment at: lib/Target/X86/X86Subtarget.h:570
 
   bool preferAVX256() const { return PreferAVX256; }
 
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This sits on top of D41096? I thought it would replace it. Do we need to prefer AVX2 if we have AVX-512 without using zmm?



https://reviews.llvm.org/D41341