[llvm] r321118 - [X86] Add an assert to indicate that there is only once specific VT allowed at a certain point in LowerMULH.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Dec 19 14:38:09 2017
New Revision: 321118

URL: http://llvm.org/viewvc/llvm-project?rev=321118&view=rev
Log:
[X86] Add an assert to indicate that there is only once specific VT allowed at a certain point in LowerMULH.

Helps with code readability a little.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=321118&r1=321117&r2=321118&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 19 14:38:09 2017
@@ -22226,6 +22226,8 @@ static SDValue LowerMULH(SDValue Op, con
                          DAG.getVectorShuffle(MVT::v16i16, dl, Lo, Hi, HiMask));
     }
 
+    assert(VT == MVT::v16i8 && "Unexpected VT");
+
     SDValue ExA = DAG.getNode(ExAVX, dl, MVT::v16i16, A);
     SDValue ExB = DAG.getNode(ExAVX, dl, MVT::v16i16, B);
     SDValue Mul = DAG.getNode(ISD::MUL, dl, MVT::v16i16, ExA, ExB);