[PATCH] D41382: [AArch64] Asm: Fix parsing of register aliases that have a name starting with 'z'

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

One more thing for completeness (there's no need to address this in this patch): currently we try to parse the register before looking up aliases so the following will fail

  	z1 .req x6
  	add z1, x0, x0
  	.unreq z1
  // CHECK: add x6, x0, x0

I think GAS tries to apply aliases first, with the following reasoning: Before the SVE registers were added, the snippet above was valid. Now it is not valid any more, as it will parse `z1` as a SVE register (the same problem also exists with NEON vector registers)


https://reviews.llvm.org/D41382