[PATCH] D41411: [PowerPC] Fix parest build failure in SPEC2017.

[Tony Jiang via Phabricator via llvm-commits]

jtony created this revision.
jtony added reviewers: nemanjai, kbarton, sfertile, syzaara, stefanp, inouehrs, lei, hfinkel, echristo.

The build failure was caused by an assertion in pre-legalization DAGCombine:

  llc: /home/jtony/src/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7232: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.

      

When it crashes, it is trying to do the following:

  Combining: t6: ppcf128 = uint_to_fp t5
  ... into: t20: f32 = PPCISD::FCFIDUS t19

  
  which is clearly wrong since ppcf128 are definitely different type with f32 and
  we cannot change the node value type when do DAGCombine. The fix is don't
  handle ppc_fp128 or i1 conversions in PPCTargetLowering::combineFPToIntToFP and
  leave it to downstream to legalize it and expand it to small legal types.
     
  Tested with 3-stage bootstrap and LNT and SPEC2017, they are functionally clean.


https://reviews.llvm.org/D41411

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll


Index: test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
@@ -0,0 +1,15 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Ensure we don't crash by trying to convert directly from a subword load
+; to a ppc_fp128 as we do for conversions to f32/f64.
+define ppc_fp128 @test(i16* nocapture readonly %Ptr) {
+entry:
+  %0 = load i16, i16* %Ptr, align 2
+  %conv = uitofp i16 %0 to ppc_fp128
+  ret ppc_fp128 %conv
+; CHECK: lhz [[LD:[0-9]+]], 0(3)
+; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
+; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
+; CHECK: bl __gcc_qadd
+}
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11882,6 +11882,12 @@
   SDLoc dl(N);
   SDValue Op(N, 0);
 
+  // Don't handle ppc_fp128 here or i1 conversions.
+  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
+    return SDValue();
+  if (Op.getOperand(0).getValueType() == MVT::i1)
+    return SDValue();
+
   SDValue FirstOperand(Op.getOperand(0));
   bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
     (FirstOperand.getValueType() == MVT::i8 ||
@@ -11910,11 +11916,6 @@
       return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld);
   }
 
-  // Don't handle ppc_fp128 here or i1 conversions.
-  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
-    return SDValue();
-  if (Op.getOperand(0).getValueType() == MVT::i1)
-    return SDValue();
 
   // For i32 intermediate values, unfortunately, the conversion functions
   // leave the upper 32 bits of the value are undefined. Within the set of


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