[llvm] r321057 - [X86] Remove unnecessary check for integer VT from combineShiftRightArithmetic.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 18 22:28:59 PST 2017


Author: ctopper
Date: Mon Dec 18 22:28:58 2017
New Revision: 321057

URL: http://llvm.org/viewvc/llvm-project?rev=321057&view=rev
Log:
[X86] Remove unnecessary check for integer VT from combineShiftRightArithmetic.

I doubt there's any way to create a ashr for an FP type.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=321057&r1=321056&r2=321057&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 18 22:28:58 2017
@@ -32551,7 +32551,7 @@ static SDValue combineShiftRightArithmet
   // 1. MOVs can write to a register that differs from source
   // 2. MOVs accept memory operands
 
-  if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
+  if (VT.isVector() || N1.getOpcode() != ISD::Constant ||
       N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
       N0.getOperand(1).getOpcode() != ISD::Constant)
     return SDValue();




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