[PATCH] D41349: Thread MCSubtargetInfo through Target::createMCAsmBackend
Rafael Avila de Espindola via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 18 14:00:13 PST 2017
LGTM
Alex Bradbury via Phabricator <reviews at reviews.llvm.org> writes:
> asb created this revision.
> asb added reviewers: craig.topper, rengolin, t.p.northover, lhames, dsanders.
> Herald added subscribers: sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar, JDevlieghere, fedor.sergeev, kbarton, kristof.beyls, arichardson, javed.absar, nhaehnle, nemanjai, sdardis, jyknight, arsenm, aemerson.
> Herald added a reviewer: JDevlieghere.
>
> Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. https://reviews.llvm.org/D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo.
>
> This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible:
>
> - Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
> - Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
> - Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
> - Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see https://reviews.llvm.org/D41221)
>
> I'm not sure who to tag as reviewer, but given this enables useful ARM and X86 cleanups I'm tagging code owners for those targets. Also Lang Hames and Daniel Sanders for touching TargetRegistry recently. Feel free to add yourself as a reviewer to tag anyone else you think would be appropriate.
>
> X86 maintainers: This currently causes some test failures related to the X86 HasNopl code which looks to me like I'm just exposing an existing bug. HasNopl is false if the CPU string is "generic", "i386", and a bunch of others. However, the CPU string is empty when passing llvm-mc arguments like `-arch=x86 -triple=i686-pc-linux-gnu`. This patch means it will be "generic", as selected by createX86MCSubtargetInfo and so HasNopl is false. CC @rafael, who last touched that HasNopl code.
>
>
> https://reviews.llvm.org/D41349
>
> Files:
> include/llvm/Support/TargetRegistry.h
> lib/CodeGen/LLVMTargetMachine.cpp
> lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
> lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
> lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
> lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
> lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
> lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
> lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
> lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
> lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
> lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
> lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
> lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
> lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
> lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
> lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
> lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> tools/dsymutil/DwarfLinker.cpp
> tools/llvm-dwp/llvm-dwp.cpp
> tools/llvm-mc/llvm-mc.cpp
> unittests/DebugInfo/DWARF/DwarfGenerator.cpp
>
> Index: unittests/DebugInfo/DWARF/DwarfGenerator.cpp
> ===================================================================
> --- unittests/DebugInfo/DWARF/DwarfGenerator.cpp
> +++ unittests/DebugInfo/DWARF/DwarfGenerator.cpp
> @@ -152,8 +152,13 @@
> MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
> MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
>
> + MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> + if (!MSTI)
> + return make_error<StringError>("no subtarget info for target " + TripleName,
> + inconvertibleErrorCode());
> +
> MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", MCOptions);
> + MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions);
> if (!MAB)
> return make_error<StringError>("no asm backend for target " + TripleName,
> inconvertibleErrorCode());
> @@ -164,11 +169,6 @@
> TripleName,
> inconvertibleErrorCode());
>
> - MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> - if (!MSTI)
> - return make_error<StringError>("no subtarget info for target " + TripleName,
> - inconvertibleErrorCode());
> -
> MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
> if (!MCE)
> return make_error<StringError>("no code emitter for target " + TripleName,
> Index: tools/llvm-mc/llvm-mc.cpp
> ===================================================================
> --- tools/llvm-mc/llvm-mc.cpp
> +++ tools/llvm-mc/llvm-mc.cpp
> @@ -567,7 +567,7 @@
> MCAsmBackend *MAB = nullptr;
> if (ShowEncoding) {
> CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
> + MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
> }
> auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
> Str.reset(TheTarget->createAsmStreamer(
> @@ -588,8 +588,7 @@
> }
>
> MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
> - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU,
> - MCOptions);
> + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
> Str.reset(TheTarget->createMCObjectStreamer(
> TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), *OS,
> std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll,
> Index: tools/llvm-dwp/llvm-dwp.cpp
> ===================================================================
> --- tools/llvm-dwp/llvm-dwp.cpp
> +++ tools/llvm-dwp/llvm-dwp.cpp
> @@ -673,20 +673,20 @@
> MCContext MC(MAI.get(), MRI.get(), &MOFI);
> MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, MC);
>
> + std::unique_ptr<MCSubtargetInfo> MSTI(
> + TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> + if (!MSTI)
> + return error("no subtarget info for target " + TripleName, Context);
> +
> MCTargetOptions Options;
> - auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
> + auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
> if (!MAB)
> return error("no asm backend for target " + TripleName, Context);
>
> std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
> if (!MII)
> return error("no instr info info for target " + TripleName, Context);
>
> - std::unique_ptr<MCSubtargetInfo> MSTI(
> - TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> - if (!MSTI)
> - return error("no subtarget info for target " + TripleName, Context);
> -
> MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC);
> if (!MCE)
> return error("no code emitter for target " + TripleName, Context);
> Index: tools/dsymutil/DwarfLinker.cpp
> ===================================================================
> --- tools/dsymutil/DwarfLinker.cpp
> +++ tools/dsymutil/DwarfLinker.cpp
> @@ -672,19 +672,19 @@
> MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
> MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
>
> + MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> + if (!MSTI)
> + return error("no subtarget info for target " + TripleName, Context);
> +
> MCTargetOptions Options;
> - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
> + MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
> if (!MAB)
> return error("no asm backend for target " + TripleName, Context);
>
> MII.reset(TheTarget->createMCInstrInfo());
> if (!MII)
> return error("no instr info info for target " + TripleName, Context);
>
> - MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
> - if (!MSTI)
> - return error("no subtarget info for target " + TripleName, Context);
> -
> MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
> if (!MCE)
> return error("no code emitter for target " + TripleName, Context);
> Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> ===================================================================
> --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> @@ -70,11 +70,13 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createX86_32AsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
> -MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createX86_64AsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> /// Implements X86-only directives for assembly emission.
> Index: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
> ===================================================================
> --- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
> +++ lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
> @@ -843,10 +843,11 @@
> } // end anonymous namespace
>
> MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TheTriple,
> - StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TheTriple = STI.getTargetTriple();
> + StringRef CPU = STI.getCPU();
> if (TheTriple.isOSBinFormatMachO())
> return new DarwinX86_32AsmBackend(T, MRI, CPU);
>
> @@ -862,10 +863,11 @@
> }
>
> MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TheTriple,
> - StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TheTriple = STI.getTargetTriple();
> + StringRef CPU = STI.getCPU();
> if (TheTriple.isOSBinFormatMachO()) {
> MachO::CPUSubTypeX86 CS =
> StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
> Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
> ===================================================================
> --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
> +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
> @@ -89,8 +89,8 @@
> MCContext &Ctx);
>
> MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter> createSystemZObjectWriter(raw_pwrite_stream &OS,
> Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
> ===================================================================
> --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
> +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
> @@ -14,6 +14,7 @@
> #include "llvm/MC/MCFixupKindInfo.h"
> #include "llvm/MC/MCInst.h"
> #include "llvm/MC/MCObjectWriter.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
>
> using namespace llvm;
>
> @@ -122,9 +123,10 @@
> }
>
> MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
> + uint8_t OSABI =
> + MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
> return new SystemZMCAsmBackend(OSABI);
> }
> Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
> ===================================================================
> --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
> +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
> @@ -40,8 +40,8 @@
> MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
> -MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
> std::unique_ptr<MCObjectWriter>
> createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
> Index: lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> ===================================================================
> --- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> +++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> @@ -14,6 +14,7 @@
> #include "llvm/MC/MCExpr.h"
> #include "llvm/MC/MCFixupKindInfo.h"
> #include "llvm/MC/MCObjectWriter.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> #include "llvm/MC/MCValue.h"
> #include "llvm/Support/TargetRegistry.h"
>
> @@ -301,8 +302,8 @@
> } // end anonymous namespace
>
> MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return new ELFSparcAsmBackend(T, TT.getOS());
> + return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
> }
> Index: lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
> ===================================================================
> --- lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
> +++ lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
> @@ -40,8 +40,8 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
> ===================================================================
> --- lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
> +++ lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
> @@ -230,9 +230,10 @@
> } // end anonymous namespace
>
> MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TT = STI.getTargetTriple();
> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
> return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
> }
> Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
> ===================================================================
> --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
> +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
> @@ -29,6 +29,7 @@
> class MCInstrInfo;
> class MCObjectWriter;
> class MCRegisterInfo;
> +class MCSubtargetInfo;
> class MCTargetOptions;
> class Target;
> class Triple;
> @@ -43,8 +44,8 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> /// Construct an PPC ELF object writer.
> Index: lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> ===================================================================
> --- lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> +++ lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
> @@ -18,6 +18,7 @@
> #include "llvm/MC/MCMachObjectWriter.h"
> #include "llvm/MC/MCObjectWriter.h"
> #include "llvm/MC/MCSectionMachO.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> #include "llvm/MC/MCSymbolELF.h"
> #include "llvm/MC/MCValue.h"
> #include "llvm/Support/ErrorHandling.h"
> @@ -231,9 +232,10 @@
> } // end anonymous namespace
>
> MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TT = STI.getTargetTriple();
> if (TT.isOSDarwin())
> return new DarwinPPCAsmBackend(T);
>
> Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
> ===================================================================
> --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
> +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
> @@ -45,8 +45,8 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
> ===================================================================
> --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
> +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
> @@ -476,8 +476,9 @@
> }
>
> MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32");
> + return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
> + Options.ABIName == "n32");
> }
> Index: lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
> ===================================================================
> --- lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
> +++ lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
> @@ -38,8 +38,8 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TheTriple, StringRef CPU,
> +MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
> ===================================================================
> --- lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
> +++ lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
> @@ -165,9 +165,10 @@
> } // namespace
>
> MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo & /*MRI*/,
> - const Triple &TT, StringRef /*CPU*/,
> const MCTargetOptions & /*Options*/) {
> + const Triple &TT = STI.getTargetTriple();
> if (!TT.isOSBinFormatELF())
> llvm_unreachable("OS not supported");
>
> Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> ===================================================================
> --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> @@ -61,8 +61,8 @@
> MCContext &MCT);
>
> MCAsmBackend *createHexagonAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> ===================================================================
> --- lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> +++ lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> @@ -765,11 +765,12 @@
>
> // MCAsmBackend
> MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
> - MCRegisterInfo const & /*MRI*/,
> - const Triple &TT, StringRef CPU,
> - const MCTargetOptions &Options) {
> + const MCSubtargetInfo &STI,
> + MCRegisterInfo const & /*MRI*/,
> + const MCTargetOptions &Options) {
> + const Triple &TT = STI.getTargetTriple();
> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
>
> - StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU);
> + StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
> return new HexagonAsmBackend(T, TT, OSABI, CPUString);
> }
> Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
> ===================================================================
> --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
> +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
> @@ -45,11 +45,11 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
> -MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter> createBPFELFObjectWriter(raw_pwrite_stream &OS,
> Index: lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
> ===================================================================
> --- lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
> +++ lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
> @@ -104,15 +104,15 @@
> }
>
> MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> - const MCTargetOptions&) {
> + const MCTargetOptions &) {
> return new BPFAsmBackend(/*IsLittleEndian=*/true);
> }
>
> MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> - const MCTargetOptions&) {
> + const MCTargetOptions &) {
> return new BPFAsmBackend(/*IsLittleEndian=*/false);
> }
> Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> ===================================================================
> --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> @@ -73,22 +73,22 @@
> const MCTargetOptions &Options,
> bool IsLittleEndian);
>
> -MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> -MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> MCAsmBackend *createThumbLEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
>
> MCAsmBackend *createThumbBEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
>
> // Construct a PE/COFF machine code streamer which will generate a PE/COFF
> Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> ===================================================================
> --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> @@ -1176,29 +1176,33 @@
> }
>
> MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
> + Options, true);
> }
>
> MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
> + Options, false);
> }
>
> MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
> + Options, true);
> }
>
> MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> - return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
> + return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
> + Options, false);
> }
> Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
> ===================================================================
> --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
> +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
> @@ -45,8 +45,9 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
>
> -MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> +MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
> ===================================================================
> --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
> +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
> @@ -198,9 +198,9 @@
> } // end anonymous namespace
>
> MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> // Use 64-bit ELF for amdgcn
> - return new ELFAMDGPUAsmBackend(T, TT);
> + return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
> }
> Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> ===================================================================
> --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> @@ -45,12 +45,12 @@
> const MCRegisterInfo &MRI,
> MCContext &Ctx);
> MCAsmBackend *createAArch64leAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
> MCAsmBackend *createAArch64beAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
>
> std::unique_ptr<MCObjectWriter>
> Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> ===================================================================
> --- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> +++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> @@ -605,10 +605,10 @@
> }
>
> MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TheTriple,
> - StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TheTriple = STI.getTargetTriple();
> if (TheTriple.isOSBinFormatMachO())
> return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
>
> @@ -624,10 +624,10 @@
> }
>
> MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TheTriple,
> - StringRef CPU,
> const MCTargetOptions &Options) {
> + const Triple &TheTriple = STI.getTargetTriple();
> assert(TheTriple.isOSBinFormatELF() &&
> "Big endian is only supported for ELF targets!");
> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
> Index: lib/CodeGen/LLVMTargetMachine.cpp
> ===================================================================
> --- lib/CodeGen/LLVMTargetMachine.cpp
> +++ lib/CodeGen/LLVMTargetMachine.cpp
> @@ -137,8 +137,7 @@
> MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
>
> MCAsmBackend *MAB =
> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
> - Options.MCOptions);
> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
> auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
> MCStreamer *S = getTarget().createAsmStreamer(
> Context, std::move(FOut), Options.MCOptions.AsmVerbose,
> @@ -152,8 +151,7 @@
> // emission fails.
> MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
> MCAsmBackend *MAB =
> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
> - Options.MCOptions);
> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
> if (!MCE || !MAB)
> return true;
>
> @@ -226,17 +224,16 @@
>
> // Create the code emitter for the target if it exists. If not, .o file
> // emission fails.
> + const MCSubtargetInfo &STI = *getMCSubtargetInfo();
> const MCRegisterInfo &MRI = *getMCRegisterInfo();
> MCCodeEmitter *MCE =
> getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
> MCAsmBackend *MAB =
> - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
> - Options.MCOptions);
> + getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
> if (!MCE || !MAB)
> return true;
>
> const Triple &T = getTargetTriple();
> - const MCSubtargetInfo &STI = *getMCSubtargetInfo();
> std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
> T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), Out,
> std::unique_ptr<MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll,
> Index: include/llvm/Support/TargetRegistry.h
> ===================================================================
> --- include/llvm/Support/TargetRegistry.h
> +++ include/llvm/Support/TargetRegistry.h
> @@ -123,8 +123,8 @@
> using AsmPrinterCtorTy = AsmPrinter *(*)(
> TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
> using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
> + const MCSubtargetInfo &STI,
> const MCRegisterInfo &MRI,
> - const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options);
> using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
> const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
> @@ -383,13 +383,12 @@
> /// createMCAsmBackend - Create a target specific assembly parser.
> ///
> /// \param TheTriple The target triple string.
> - MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
> - StringRef TheTriple, StringRef CPU,
> - const MCTargetOptions &Options)
> - const {
> + MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> + const MCTargetOptions &Options) const {
> if (!MCAsmBackendCtorFn)
> return nullptr;
> - return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options);
> + return MCAsmBackendCtorFn(*this, STI, MRI, Options);
> }
>
> /// createMCAsmParser - Create a target specific assembly parser.
> @@ -1106,10 +1105,10 @@
> }
>
> private:
> - static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
> - const Triple &TheTriple, StringRef CPU,
> + static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
> + const MCRegisterInfo &MRI,
> const MCTargetOptions &Options) {
> - return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
> + return new MCAsmBackendImpl(T, STI, MRI);
> }
> };
>
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