[PATCH] D41350: [DAGCombine] Improve ReduceLoadWidth for SRL

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/X86/h-registers-1.ll:18
+; CHECK: movq   %r9, %r
 ; CHECK: movzbl %{{[abcd]}}h, %e
 ; CHECK: ret
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These checks aren't testing the zero-extension. I've updated the test at rL321003 - please can you rebase and then regenerate the test with the update_llc_test_checks.py script to check the diff?


https://reviews.llvm.org/D41350