[llvm] r321003 - [X86] Regenerate test to improve codegen testing for D41350

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Dec 18 10:31:02 2017
New Revision: 321003

URL: http://llvm.org/viewvc/llvm-project?rev=321003&view=rev
Log:
[X86] Regenerate test to improve codegen testing for D41350

Modified:
    llvm/trunk/test/CodeGen/X86/h-registers-1.ll

Modified: llvm/trunk/test/CodeGen/X86/h-registers-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-1.ll?rev=321003&r1=321002&r2=321003&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-registers-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-registers-1.ll Mon Dec 18 10:31:02 2017
@@ -1,24 +1,84 @@
-; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux | FileCheck %s
-; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=-bmi | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=-bmi | FileCheck %s --check-prefix=GNUX32
 
 ; LLVM creates virtual registers for values live across blocks
 ; based on the type of the value. Make sure that the extracts
 ; here use the GR64_NOREX register class for their result,
 ; instead of plain GR64.
 
-; CHECK: foo:
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: movzbl %{{[abcd]}}h, %e
-; CHECK: ret
-
-define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d,
-                i64 %e, i64 %f, i64 %g, i64 %h) {
+define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 24
+; CHECK-NEXT:    .cfi_offset %rbx, -24
+; CHECK-NEXT:    .cfi_offset %rbp, -16
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    movzbl %bh, %esi # NOREX
+; CHECK-NEXT:    movzbl %ah, %eax # NOREX
+; CHECK-NEXT:    movq %rax, %r10
+; CHECK-NEXT:    movzbl %dh, %edx # NOREX
+; CHECK-NEXT:    movzbl %ch, %eax # NOREX
+; CHECK-NEXT:    movq %rax, %r11
+; CHECK-NEXT:    movq %r8, %rax
+; CHECK-NEXT:    movzbl %ah, %ecx # NOREX
+; CHECK-NEXT:    movq %r9, %rax
+; CHECK-NEXT:    movzbl %ah, %ebp # NOREX
+; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT:    movzbl %ah, %eax # NOREX
+; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %ebx
+; CHECK-NEXT:    movzbl %bh, %edi # NOREX
+; CHECK-NEXT:    movq %r10, %r8
+; CHECK-NEXT:    addq %r8, %rsi
+; CHECK-NEXT:    addq %r11, %rdx
+; CHECK-NEXT:    addq %rsi, %rdx
+; CHECK-NEXT:    addq %rbp, %rcx
+; CHECK-NEXT:    addq %rdi, %rax
+; CHECK-NEXT:    addq %rcx, %rax
+; CHECK-NEXT:    addq %rdx, %rax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+;
+; GNUX32-LABEL: foo:
+; GNUX32:       # %bb.0:
+; GNUX32-NEXT:    pushq %rbp
+; GNUX32-NEXT:    .cfi_def_cfa_offset 16
+; GNUX32-NEXT:    pushq %rbx
+; GNUX32-NEXT:    .cfi_def_cfa_offset 24
+; GNUX32-NEXT:    .cfi_offset %rbx, -24
+; GNUX32-NEXT:    .cfi_offset %rbp, -16
+; GNUX32-NEXT:    movq %rsi, %rax
+; GNUX32-NEXT:    movq %rdi, %rbx
+; GNUX32-NEXT:    movzbl %bh, %esi # NOREX
+; GNUX32-NEXT:    movzbl %ah, %eax # NOREX
+; GNUX32-NEXT:    movq %rax, %r10
+; GNUX32-NEXT:    movzbl %dh, %edx # NOREX
+; GNUX32-NEXT:    movzbl %ch, %eax # NOREX
+; GNUX32-NEXT:    movq %rax, %r11
+; GNUX32-NEXT:    movq %r8, %rax
+; GNUX32-NEXT:    movzbl %ah, %ecx # NOREX
+; GNUX32-NEXT:    movq %r9, %rax
+; GNUX32-NEXT:    movzbl %ah, %ebp # NOREX
+; GNUX32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GNUX32-NEXT:    movzbl %ah, %eax # NOREX
+; GNUX32-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; GNUX32-NEXT:    movzbl %bh, %edi # NOREX
+; GNUX32-NEXT:    movq %r10, %r8
+; GNUX32-NEXT:    addq %r8, %rsi
+; GNUX32-NEXT:    addq %r11, %rdx
+; GNUX32-NEXT:    addq %rsi, %rdx
+; GNUX32-NEXT:    addq %rbp, %rcx
+; GNUX32-NEXT:    addq %rdi, %rax
+; GNUX32-NEXT:    addq %rcx, %rax
+; GNUX32-NEXT:    addq %rdx, %rax
+; GNUX32-NEXT:    popq %rbx
+; GNUX32-NEXT:    popq %rbp
+; GNUX32-NEXT:    retq
   %sa = lshr i64 %a, 8
   %A = and i64 %sa, 255
   %sb = lshr i64 %b, 8