[PATCH] D41221: [RISCV] writeNopData support generate c.nop

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Creating a TgtMCSubtargetInfo without passing CPUName and FeatureString is what ARM does in ARMAsmBackend, but it seems pretty confusing. The fact that the desired behaviour doesn't work with -triple riscv32 -mattr=+c indicates to me that something is wrong.

https://reviews.llvm.org/D20830 added an MCSubtargetInfo parameter to relaxInstruction. I could see that the same justification could be used to add MCSubtargetInfo to writeNopData.

Does anyone else have views on this? It's been a while since I stepped through the TargetRegistry code - if feasible, having a properly initialised RISCVMCSubtargetInfo (with cpustring and featurestring set correctly) as a field of RISCVAsmBackend seems ideal, but from an initial look it might be difficult.


Repository:
  rL LLVM

https://reviews.llvm.org/D41221