[PATCH] D41341: [X86] WIP disable 512-bit vectors during type legalization for prefer-vector-width

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: hfinkel, spatel, RKSimon.

This continues the work started in https://reviews.llvm.org/D41096

This patch adds a new subtarget feature to indicate that there are no 512-bit vectors present in the function. When combined the prefer-avx256 feature, it will disable 512-bit vectors in the legalizer. I intend to set this subtarget feature in getSubtargetImpl when the Function has a function attribute indicating the required vector width for the function is less than 512 bits.

I looked into trying to add a 512-bit register feature that could be disabled instead like https://reviews.llvm.org/D41096 proposed, but I couldn't find a good way to make the existing command line options work. The tablegen generated subtarget feature system just doesn't allow for a wrapper/alias feature that implies other features.

I had to allow VK32 to be legal with BWI and (VLX || 512-bit vectors). VK64 is only legal with BWI and 512-bit vectors. VK64 is only needed when v64i8 is legal.

I know there are still places in the code that extend narrow vectors to 512-bit to do an operation on wider vector elements and truncate back. Those will need to be split before extending instead.

I plan to add some basic tests for this as well and I'll be adding tests as I fix the various extending lowerings mentioned above.


https://reviews.llvm.org/D41341

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h

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