[llvm] r320924 - [X86] Combine some more scheduler model entries using regular expressions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 16 10:35:31 PST 2017
Author: ctopper
Date: Sat Dec 16 10:35:31 2017
New Revision: 320924
URL: http://llvm.org/viewvc/llvm-project?rev=320924&view=rev
Log:
[X86] Combine some more scheduler model entries using regular expressions.
We had a lot of separate 32 and 64 instructions that had the same scheduling data. This merges them into the same regular expression. This is pretty consistent with a lot of other instructions.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=320924&r1=320923&r2=320924&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Dec 16 10:35:31 2017
@@ -596,10 +596,8 @@ def BWWriteResGroup6 : SchedWriteRes<[BW
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr(_REV)?")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADCX32rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADCX64rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADOX32rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADOX64rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADCX(32|64)rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADOX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8")>;
def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "BTC(16|32|64)ri8")>;
@@ -658,14 +656,12 @@ def: InstRW<[BWWriteResGroup6], (instreg
def: InstRW<[BWWriteResGroup6], (instregex "JP_4")>;
def: InstRW<[BWWriteResGroup6], (instregex "JS_1")>;
def: InstRW<[BWWriteResGroup6], (instregex "JS_4")>;
-def: InstRW<[BWWriteResGroup6], (instregex "RORX32ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "RORX64ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "RORX(32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SARX32rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SARX64rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SARX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr(_REV)?")>;
@@ -687,30 +683,23 @@ def: InstRW<[BWWriteResGroup6], (instreg
def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL8ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHLX32rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHLX64rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHLX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR8ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHRX32rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHRX64rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHRX(32|64)rr")>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup7], (instregex "ANDN32rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "ANDN64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSI32rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSI64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSMSK32rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSMSK64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSR32rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "BLSI(32|64)rr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "BLSMSK(32|64)rr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "BLSR(32|64)rr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "BZHI(32|64)rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;
@@ -1178,8 +1167,7 @@ def BWWriteResGroup19 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup19], (instregex "BEXTR32rr")>;
-def: InstRW<[BWWriteResGroup19], (instregex "BEXTR64rr")>;
+def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr")>;
def: InstRW<[BWWriteResGroup19], (instregex "BSWAP(16|32|64)r")>;
def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
@@ -1315,10 +1303,8 @@ def: InstRW<[BWWriteResGroup27], (instre
def: InstRW<[BWWriteResGroup27], (instregex "MIN(C?)SSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr")>;
def: InstRW<[BWWriteResGroup27], (instregex "MUL8r")>;
-def: InstRW<[BWWriteResGroup27], (instregex "PDEP32rr")>;
-def: InstRW<[BWWriteResGroup27], (instregex "PDEP64rr")>;
-def: InstRW<[BWWriteResGroup27], (instregex "PEXT32rr")>;
-def: InstRW<[BWWriteResGroup27], (instregex "PEXT64rr")>;
+def: InstRW<[BWWriteResGroup27], (instregex "PDEP(32|64)rr")>;
+def: InstRW<[BWWriteResGroup27], (instregex "PEXT(32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "POPCNT(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[BWWriteResGroup27], (instregex "SHRD(16|32|64)rri8")>;
@@ -2086,10 +2072,8 @@ def BWWriteResGroup63 : SchedWriteRes<[B
}
def: InstRW<[BWWriteResGroup63], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADC8rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "ADCX32rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "ADCX64rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "ADOX32rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "ADOX64rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "ADCX(32|64)rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "ADOX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOVAE(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOVB(16|32|64)rm")>;
@@ -2105,32 +2089,23 @@ def: InstRW<[BWWriteResGroup63], (instre
def: InstRW<[BWWriteResGroup63], (instregex "CMOVO(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOVP(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOVS(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "RORX32mi")>;
-def: InstRW<[BWWriteResGroup63], (instregex "RORX64mi")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SARX32rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SARX64rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "RORX(32|64)mi")>;
+def: InstRW<[BWWriteResGroup63], (instregex "SARX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SBB8rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SHLX32rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SHLX64rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SHRX32rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SHRX64rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "SHLX(32|64)rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "SHRX(32|64)rm")>;
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup64], (instregex "ANDN32rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "ANDN64rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSI32rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSI64rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK32rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK64rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSR32rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BLSR64rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BZHI32rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "BZHI64rm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "BLSI(32|64)rm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK(32|64)rm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "BLSR(32|64)rm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "BZHI(32|64)rm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSBrm64")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSDrm64")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSWrm64")>;
@@ -2620,8 +2595,7 @@ def BWWriteResGroup85 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup85], (instregex "BEXTR32rm")>;
-def: InstRW<[BWWriteResGroup85], (instregex "BEXTR64rm")>;
+def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
let Latency = 7;
@@ -2707,10 +2681,8 @@ def: InstRW<[BWWriteResGroup91], (instre
def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTTPS2PIirm")>;
def: InstRW<[BWWriteResGroup91], (instregex "MUL64m")>;
def: InstRW<[BWWriteResGroup91], (instregex "MUL8m")>;
-def: InstRW<[BWWriteResGroup91], (instregex "PDEP32rm")>;
-def: InstRW<[BWWriteResGroup91], (instregex "PDEP64rm")>;
-def: InstRW<[BWWriteResGroup91], (instregex "PEXT32rm")>;
-def: InstRW<[BWWriteResGroup91], (instregex "PEXT64rm")>;
+def: InstRW<[BWWriteResGroup91], (instregex "PDEP(32|64)rm")>;
+def: InstRW<[BWWriteResGroup91], (instregex "PEXT(32|64)rm")>;
def: InstRW<[BWWriteResGroup91], (instregex "POPCNT(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup91], (instregex "SUBPDrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "SUBPSrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=320924&r1=320923&r2=320924&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Dec 16 10:35:31 2017
@@ -1205,14 +1205,12 @@ def: InstRW<[HWWriteResGroup7], (instreg
def: InstRW<[HWWriteResGroup7], (instregex "JP_4")>;
def: InstRW<[HWWriteResGroup7], (instregex "JS_1")>;
def: InstRW<[HWWriteResGroup7], (instregex "JS_4")>;
-def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>;
-def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>;
+def: InstRW<[HWWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>;
+def: InstRW<[HWWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>;
@@ -1231,30 +1229,23 @@ def: InstRW<[HWWriteResGroup7], (instreg
def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>;
+def: InstRW<[HWWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>;
-def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>;
+def: InstRW<[HWWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "BLSI(32|64)rr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK(32|64)rr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "BLSR(32|64)rr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "BZHI(32|64)rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
@@ -1610,10 +1601,8 @@ def: InstRW<[HWWriteResGroup12], (instre
def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTTPS2PIirm")>;
def: InstRW<[HWWriteResGroup12], (instregex "MUL(16|32|64)m")>;
def: InstRW<[HWWriteResGroup12], (instregex "MUL8m")>;
-def: InstRW<[HWWriteResGroup12], (instregex "PDEP32rm")>;
-def: InstRW<[HWWriteResGroup12], (instregex "PDEP64rm")>;
-def: InstRW<[HWWriteResGroup12], (instregex "PEXT32rm")>;
-def: InstRW<[HWWriteResGroup12], (instregex "PEXT64rm")>;
+def: InstRW<[HWWriteResGroup12], (instregex "PDEP(32|64)rm")>;
+def: InstRW<[HWWriteResGroup12], (instregex "PEXT(32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "POPCNT(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "SUBSDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "SUBSSrm")>;
@@ -1840,16 +1829,11 @@ def HWWriteResGroup16 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup16], (instregex "ANDN32rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "ANDN64rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSI32rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSI64rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK32rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK64rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSR32rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BLSR64rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BZHI32rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "BZHI64rm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "BLSI(32|64)rm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK(32|64)rm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "BLSR(32|64)rm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "BZHI(32|64)rm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSBrm64")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSDrm64")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSWrm64")>;
@@ -2349,8 +2333,7 @@ def HWWriteResGroup34 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup34], (instregex "BEXTR32rr")>;
-def: InstRW<[HWWriteResGroup34], (instregex "BEXTR64rr")>;
+def: InstRW<[HWWriteResGroup34], (instregex "BEXTR(32|64)rr")>;
def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
@@ -2489,8 +2472,7 @@ def HWWriteResGroup42 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup42], (instregex "BEXTR32rm")>;
-def: InstRW<[HWWriteResGroup42], (instregex "BEXTR64rm")>;
+def: InstRW<[HWWriteResGroup42], (instregex "BEXTR(32|64)rm")>;
def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let Latency = 7;
@@ -2615,10 +2597,8 @@ def: InstRW<[HWWriteResGroup50], (instre
def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)SSrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr")>;
def: InstRW<[HWWriteResGroup50], (instregex "MUL8r")>;
-def: InstRW<[HWWriteResGroup50], (instregex "PDEP32rr")>;
-def: InstRW<[HWWriteResGroup50], (instregex "PDEP64rr")>;
-def: InstRW<[HWWriteResGroup50], (instregex "PEXT32rr")>;
-def: InstRW<[HWWriteResGroup50], (instregex "PEXT64rr")>;
+def: InstRW<[HWWriteResGroup50], (instregex "PDEP(32|64)rr")>;
+def: InstRW<[HWWriteResGroup50], (instregex "PEXT(32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "POPCNT(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[HWWriteResGroup50], (instregex "SHRD(16|32|64)rri8")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=320924&r1=320923&r2=320924&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Dec 16 10:35:31 2017
@@ -704,10 +704,8 @@ def SKLWriteResGroup7 : SchedWriteRes<[S
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADCX64rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADOX32rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADOX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADCX(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADOX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;
@@ -767,14 +765,12 @@ def: InstRW<[SKLWriteResGroup7], (instre
def: InstRW<[SKLWriteResGroup7], (instregex "JP_4")>;
def: InstRW<[SKLWriteResGroup7], (instregex "JS_1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "JS_4")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "RORX32ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "RORX64ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
@@ -796,14 +792,12 @@ def: InstRW<[SKLWriteResGroup7], (instre
def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SHLX32rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SHLX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SHRX32rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SHRX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "STAC")>;
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
@@ -811,16 +805,11 @@ def SKLWriteResGroup8 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup8], (instregex "ANDN32rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "ANDN64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSI32rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSI64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK32rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSR32rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSI(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSR(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BZHI(32|64)rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
@@ -1210,8 +1199,7 @@ def SKLWriteResGroup22 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR32rr")>;
-def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR64rr")>;
+def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR(32|64)rr")>;
def: InstRW<[SKLWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;
def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
@@ -1301,10 +1289,8 @@ def: InstRW<[SKLWriteResGroup29], (instr
def: InstRW<[SKLWriteResGroup29], (instregex "IMUL8r")>;
def: InstRW<[SKLWriteResGroup29], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "MUL8r")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "PDEP32rr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "PDEP64rr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "PEXT32rr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "PEXT64rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PEXT(32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "POPCNT(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup29], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[SKLWriteResGroup29], (instregex "SHRD(16|32|64)rri8")>;
@@ -2077,10 +2063,8 @@ def SKLWriteResGroup74 : SchedWriteRes<[
}
def: InstRW<[SKLWriteResGroup74], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADC8rm")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "ADCX32rm")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "ADCX64rm")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "ADOX32rm")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "ADOX64rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADCX(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADOX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup74], (instregex "CMOVAE(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "CMOVB(16|32|64)rm")>;
@@ -2112,16 +2096,11 @@ def SKLWriteResGroup75 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup75], (instregex "ANDN32rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "ANDN64rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSI32rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSI64rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK32rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK64rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSR32rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BLSR64rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BZHI32rm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "BZHI64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSI(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSR(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BZHI(32|64)rm")>;
def: InstRW<[SKLWriteResGroup75], (instregex "MOVBE(16|32|64)rm")>;
def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
@@ -2603,8 +2582,7 @@ def SKLWriteResGroup99 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR32rm")>;
-def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR64rm")>;
+def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR(32|64)rm")>;
def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 7;
@@ -2691,10 +2669,8 @@ def: InstRW<[SKLWriteResGroup107], (inst
def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "MUL(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup107], (instregex "MUL8m")>;
-def: InstRW<[SKLWriteResGroup107], (instregex "PDEP32rm")>;
-def: InstRW<[SKLWriteResGroup107], (instregex "PDEP64rm")>;
-def: InstRW<[SKLWriteResGroup107], (instregex "PEXT32rm")>;
-def: InstRW<[SKLWriteResGroup107], (instregex "PEXT64rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PEXT(32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "POPCNT(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "TZCNT(16|32|64)rm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=320924&r1=320923&r2=320924&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Dec 16 10:35:31 2017
@@ -1008,10 +1008,8 @@ def SKXWriteResGroup7 : SchedWriteRes<[S
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr(_REV)?")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "ADCX32rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "ADCX64rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "ADOX32rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "ADOX64rr")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "ADCX(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "ADOX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;
@@ -1071,14 +1069,12 @@ def: InstRW<[SKXWriteResGroup7], (instre
def: InstRW<[SKXWriteResGroup7], (instregex "JP_4")>;
def: InstRW<[SKXWriteResGroup7], (instregex "JS_1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "JS_4")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "RORX32ri")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "RORX64ri")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR8ri")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SARX32rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SARX64rr")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV)?")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr(_REV)?")>;
@@ -1100,14 +1096,12 @@ def: InstRW<[SKXWriteResGroup7], (instre
def: InstRW<[SKXWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL8ri")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SHLX32rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SHLX64rr")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR8ri")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SHRX32rr")>;
-def: InstRW<[SKXWriteResGroup7], (instregex "SHRX64rr")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "STAC")>;
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
@@ -1115,16 +1109,11 @@ def SKXWriteResGroup8 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup8], (instregex "ANDN32rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "ANDN64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSI32rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSI64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSMSK32rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSMSK64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSR32rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BLSR64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BZHI32rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "BZHI64rr")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "BLSI(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "BLSMSK(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "BLSR(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "BZHI(32|64)rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
@@ -1720,8 +1709,7 @@ def SKXWriteResGroup22 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup22], (instregex "BEXTR32rr")>;
-def: InstRW<[SKXWriteResGroup22], (instregex "BEXTR64rr")>;
+def: InstRW<[SKXWriteResGroup22], (instregex "BEXTR(32|64)rr")>;
def: InstRW<[SKXWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;
def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
@@ -1845,10 +1833,8 @@ def: InstRW<[SKXWriteResGroup31], (instr
def: InstRW<[SKXWriteResGroup31], (instregex "IMUL8r")>;
def: InstRW<[SKXWriteResGroup31], (instregex "LZCNT(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "MUL8r")>;
-def: InstRW<[SKXWriteResGroup31], (instregex "PDEP32rr")>;
-def: InstRW<[SKXWriteResGroup31], (instregex "PDEP64rr")>;
-def: InstRW<[SKXWriteResGroup31], (instregex "PEXT32rr")>;
-def: InstRW<[SKXWriteResGroup31], (instregex "PEXT64rr")>;
+def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr")>;
+def: InstRW<[SKXWriteResGroup31], (instregex "PEXT(32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "POPCNT(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup31], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[SKXWriteResGroup31], (instregex "SHRD(16|32|64)rri8")>;
@@ -3261,10 +3247,8 @@ def SKXWriteResGroup78 : SchedWriteRes<[
}
def: InstRW<[SKXWriteResGroup78], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "ADC8rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "ADCX32rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "ADCX64rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "ADOX32rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "ADOX64rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "ADCX(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "ADOX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup78], (instregex "CMOVAE(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "CMOVB(16|32|64)rm")>;
@@ -3280,32 +3264,23 @@ def: InstRW<[SKXWriteResGroup78], (instr
def: InstRW<[SKXWriteResGroup78], (instregex "CMOVO(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "CMOVP(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "CMOVS(16|32|64)rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "RORX32mi")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "RORX64mi")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SARX32rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SARX64rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "RORX(32|64)mi")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "SARX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SBB8rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SHLX32rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SHLX64rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SHRX32rm")>;
-def: InstRW<[SKXWriteResGroup78], (instregex "SHRX64rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "SHLX(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "SHRX(32|64)rm")>;
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup79], (instregex "ANDN32rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "ANDN64rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSI32rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSI64rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSMSK32rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSMSK64rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSR32rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BLSR64rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BZHI32rm")>;
-def: InstRW<[SKXWriteResGroup79], (instregex "BZHI64rm")>;
+def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup79], (instregex "BLSI(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup79], (instregex "BLSMSK(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup79], (instregex "BLSR(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup79], (instregex "BZHI(32|64)rm")>;
def: InstRW<[SKXWriteResGroup79], (instregex "MOVBE(16|32|64)rm")>;
def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
@@ -3999,8 +3974,7 @@ def SKXWriteResGroup105 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup105], (instregex "BEXTR32rm")>;
-def: InstRW<[SKXWriteResGroup105], (instregex "BEXTR64rm")>;
+def: InstRW<[SKXWriteResGroup105], (instregex "BEXTR(32|64)rm")>;
def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 7;
@@ -4153,10 +4127,8 @@ def: InstRW<[SKXWriteResGroup118], (inst
def: InstRW<[SKXWriteResGroup118], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "MUL(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup118], (instregex "MUL8m")>;
-def: InstRW<[SKXWriteResGroup118], (instregex "PDEP32rm")>;
-def: InstRW<[SKXWriteResGroup118], (instregex "PDEP64rm")>;
-def: InstRW<[SKXWriteResGroup118], (instregex "PEXT32rm")>;
-def: InstRW<[SKXWriteResGroup118], (instregex "PEXT64rm")>;
+def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup118], (instregex "PEXT(32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "POPCNT(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup118], (instregex "TZCNT(16|32|64)rm")>;
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