[PATCH] D41126: [SelectionDAG] Fixed f16-from-vector promotion problem

[Tim Renouf via Phabricator via llvm-commits]

tpr updated this revision to Diff 127244.
tpr added a comment.

V2: The fix is now to avoid vector scalarization creating a v1->scalar bitcast.


https://reviews.llvm.org/D41126

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  test/CodeGen/AMDGPU/unpack-half.ll


Index: test/CodeGen/AMDGPU/unpack-half.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/unpack-half.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+
+; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the
+; extension of a vector of f16 generates an illegal node that errors later.
+
+; FUNC-LABEL: {{^}}main:
+; CHECK: v_cvt_f32_f16
+
+define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 {
+.entry:
+  %tmp = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 0, i32 undef, i1 true, i1 true) #1
+  %tmp1 = bitcast float %tmp to i32
+  %im0.i = lshr i32 %tmp1, 16
+  %tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1
+  %tmp3 = trunc <2 x i32> %tmp2 to <2 x i16>
+  %tmp4 = bitcast <2 x i16> %tmp3 to <2 x half>
+  %tmp5 = fpext <2 x half> %tmp4 to <2 x float>
+  %bc = bitcast <2 x float> %tmp5 to <2 x i32>
+  %tmp6 = extractelement <2 x i32> %bc, i32 1
+  call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp6, <4 x i32> undef, i32 0, i32 4, i32 %arg, i32 0, i32 4, i32 4, i1 true, i1 true) #0
+  ret void
+}
+
+declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
+
+declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #0
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+
Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -169,9 +169,13 @@
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
+  SDValue Op = N->getOperand(0);
+  if (Op.getValueType().isVector()
+      && Op.getValueType().getVectorNumElements() == 1)
+    Op = GetScalarizedVector(Op);
   EVT NewVT = N->getValueType(0).getVectorElementType();
   return DAG.getNode(ISD::BITCAST, SDLoc(N),
-                     NewVT, N->getOperand(0));
+                     NewVT, Op);
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {


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