[llvm] r320799 - [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 15 02:20:51 PST 2017
Author: asb
Date: Fri Dec 15 02:20:51 2017
New Revision: 320799
URL: http://llvm.org/viewvc/llvm-project?rev=320799&view=rev
Log:
[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.
Differential Revision: https://reviews.llvm.org/D41216
Patch by Shiva Chen.
Modified:
llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/trunk/test/MC/RISCV/rv32c-invalid.s
llvm/trunk/test/MC/RISCV/rv64c-invalid.s
llvm/trunk/test/MC/RISCV/rv64c-valid.s
Modified: llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp?rev=320799&r1=320798&r2=320799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp Fri Dec 15 02:20:51 2017
@@ -216,6 +216,18 @@ public:
return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
}
+ bool isUImmLog2XLenNonZero() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK;
+ if (!isImm())
+ return false;
+ if (!evaluateConstantImm(Imm, VK) || VK != RISCVMCExpr::VK_RISCV_None)
+ return false;
+ if (Imm == 0)
+ return false;
+ return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
+ }
+
bool isUImm5() const {
int64_t Imm;
RISCVMCExpr::VariantKind VK;
@@ -592,10 +604,12 @@ bool RISCVAsmParser::MatchAndEmitInstruc
if (isRV64())
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
+ case Match_InvalidUImmLog2XLenNonZero:
+ if (isRV64())
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
case Match_InvalidUImm5:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
- case Match_InvalidUImm5NonZero:
- return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
case Match_InvalidSImm6:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
(1 << 5) - 1);
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=320799&r1=320798&r2=320799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Fri Dec 15 02:20:51 2017
@@ -13,10 +13,20 @@ include "RISCVInstrFormatsC.td"
// Operand definitions.
//===----------------------------------------------------------------------===//
-def uimm5nonzero : Operand<XLenVT>,
- ImmLeaf<XLenVT, [{return isUInt<5>(Imm) && (Imm != 0);}]> {
- let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
- let DecoderMethod = "decodeUImmOperand<5>";
+def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
+ let Name = "UImmLog2XLenNonZero";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidUImmLog2XLenNonZero";
+}
+
+def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
+}]> {
+ let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
+ // TODO: should ensure invalid shamt is rejected when decoding.
+ let DecoderMethod = "decodeUImmOperand<6>";
}
def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
@@ -290,8 +300,8 @@ def C_LUI : RVInst16CI<0b011, 0b01, (out
let Inst{6-2} = imm{4-0};
}
-def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimm5nonzero>;
-def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimm5nonzero>;
+def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>;
+def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
@@ -323,7 +333,7 @@ def C_BNEZ : Bcz<0b111, "c.bnez", setne
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
- (ins GPRNoX0:$rd, uimm5nonzero:$imm),
+ (ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
"c.slli" ,"$rd, $imm"> {
let Constraints = "$rd = $rd_wb";
let Inst{6-2} = imm{4-0};
Modified: llvm/trunk/test/MC/RISCV/rv32c-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32c-invalid.s?rev=320799&r1=320798&r2=320799&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32c-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32c-invalid.s Fri Dec 15 02:20:51 2017
@@ -38,7 +38,7 @@ c.addi16sp t0, 16 # CHECK: :[[@LINE]]:1
# Out of range immediates
-## uimm5nonzero
+## uimmlog2xlennonzero
c.slli t0, 64 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
c.srli a0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
c.srai a0, 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
Modified: llvm/trunk/test/MC/RISCV/rv64c-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64c-invalid.s?rev=320799&r1=320798&r2=320799&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64c-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64c-invalid.s Fri Dec 15 02:20:51 2017
@@ -12,6 +12,11 @@ c.ldsp zero, 4(sp) # CHECK: :[[@LINE]]:
# Out of range immediates
+## uimmlog2xlennonzero
+c.slli t0, 64 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+c.srli a0, -1 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+c.srai a0, 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+
## simm6
c.addiw t0, -33 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
c.addiw t0, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
Modified: llvm/trunk/test/MC/RISCV/rv64c-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64c-valid.s?rev=320799&r1=320798&r2=320799&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64c-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64c-valid.s Fri Dec 15 02:20:51 2017
@@ -32,3 +32,13 @@ c.addiw a3, -32
# CHECK-INST: c.addiw a3, 31
# CHECK: encoding: [0xfd,0x26]
c.addiw a3, 31
+
+# CHECK-INST: c.slli s0, 1
+# CHECK: encoding: [0x06,0x04]
+c.slli s0, 1
+# CHECK-INST: c.srli a3, 63
+# CHECK: encoding: [0xfd,0x92]
+c.srli a3, 63
+# CHECK-INST: c.srai a2, 63
+# CHECK: encoding: [0x7d,0x96]
+c.srai a2, 63
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