[llvm] r320790 - [X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 23:16:41 PST 2017
Author: ctopper
Date: Thu Dec 14 23:16:41 2017
New Revision: 320790
URL: http://llvm.org/viewvc/llvm-project?rev=320790&view=rev
Log:
[X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.
A couple places didn't use the same SDValue variables to connect everything all the way through.
I don't have a test case for a bug in insert into the lower bits of a non-zero, non-undef vector. Not sure the best way to create that. We don't create the case when lowering concat_vectors which is the main way to get insert_subvectors.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=320790&r1=320789&r2=320790&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 14 23:16:41 2017
@@ -5101,9 +5101,8 @@ static SDValue insert1BitVector(SDValue
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
getZeroVector(WideOpVT, Subtarget, DAG, dl),
SubVec, ZeroIdx);
- Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op,
- ZeroIdx);
+ Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
}
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
@@ -5111,9 +5110,9 @@ static SDValue insert1BitVector(SDValue
if (Vec.isUndef()) {
assert(IdxVal != 0 && "Unexpected index");
- Op = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
- DAG.getConstant(IdxVal, dl, MVT::i8));
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
+ SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
+ DAG.getConstant(IdxVal, dl, MVT::i8));
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
}
if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
@@ -5123,9 +5122,10 @@ static SDValue insert1BitVector(SDValue
unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
DAG.getConstant(ShiftLeft, dl, MVT::i8));
- Op = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Op,
- DAG.getConstant(ShiftRight, dl, MVT::i8));
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
+ if (ShiftRight != 0)
+ SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
+ DAG.getConstant(ShiftRight, dl, MVT::i8));
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
}
// Simple case when we put subvector in the upper part
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll?rev=320790&r1=320789&r2=320790&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll Thu Dec 14 23:16:41 2017
@@ -43844,3 +43844,56 @@ define i32 @test_cmpm_rnd_zero(<16 x flo
%cast2 = bitcast <32 x i1> %shuffle to i32
ret i32 %cast2
}
+
+define i8 @mask_zero_lower(<4 x i32> %a) {
+; VLX-LABEL: mask_zero_lower:
+; VLX: # %bb.0:
+; VLX-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
+; VLX-NEXT: kshiftlb $4, %k0, %k0
+; VLX-NEXT: kmovd %k0, %eax
+; VLX-NEXT: # kill: def %al killed %al killed %eax
+; VLX-NEXT: retq
+;
+; NoVLX-LABEL: mask_zero_lower:
+; NoVLX: # %bb.0:
+; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
+; NoVLX-NEXT: vpextrb $4, %xmm0, %eax
+; NoVLX-NEXT: kmovw %eax, %k0
+; NoVLX-NEXT: vpextrb $0, %xmm0, %eax
+; NoVLX-NEXT: kmovw %eax, %k1
+; NoVLX-NEXT: kxorw %k0, %k0, %k2
+; NoVLX-NEXT: kshiftrw $4, %k2, %k3
+; NoVLX-NEXT: kxorw %k1, %k3, %k1
+; NoVLX-NEXT: kshiftlw $15, %k1, %k1
+; NoVLX-NEXT: kshiftrw $11, %k1, %k1
+; NoVLX-NEXT: kxorw %k2, %k1, %k1
+; NoVLX-NEXT: kshiftrw $5, %k1, %k2
+; NoVLX-NEXT: kxorw %k0, %k2, %k0
+; NoVLX-NEXT: kshiftlw $15, %k0, %k0
+; NoVLX-NEXT: kshiftrw $10, %k0, %k0
+; NoVLX-NEXT: kxorw %k1, %k0, %k0
+; NoVLX-NEXT: kshiftrw $6, %k0, %k1
+; NoVLX-NEXT: vpextrb $8, %xmm0, %eax
+; NoVLX-NEXT: kmovw %eax, %k2
+; NoVLX-NEXT: kxorw %k2, %k1, %k1
+; NoVLX-NEXT: kshiftlw $15, %k1, %k1
+; NoVLX-NEXT: kshiftrw $9, %k1, %k1
+; NoVLX-NEXT: kxorw %k0, %k1, %k0
+; NoVLX-NEXT: kshiftrw $7, %k0, %k1
+; NoVLX-NEXT: vpextrb $12, %xmm0, %eax
+; NoVLX-NEXT: kmovw %eax, %k2
+; NoVLX-NEXT: kxorw %k2, %k1, %k1
+; NoVLX-NEXT: kshiftlw $15, %k1, %k1
+; NoVLX-NEXT: kshiftrw $8, %k1, %k1
+; NoVLX-NEXT: kxorw %k0, %k1, %k0
+; NoVLX-NEXT: kmovw %k0, %eax
+; NoVLX-NEXT: # kill: def %al killed %al killed %eax
+; NoVLX-NEXT: retq
+ %cmp = icmp ult <4 x i32> %a, zeroinitializer
+ %concat = shufflevector <4 x i1> %cmp, <4 x i1> zeroinitializer, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+ %cast = bitcast <8 x i1> %concat to i8
+ ret i8 %cast
+}
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