[llvm] r320746 - DAG: Expose all MMO flags in getTgtMemIntrinsic
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 13:39:51 PST 2017
Author: arsenm
Date: Thu Dec 14 13:39:51 2017
New Revision: 320746
URL: http://llvm.org/viewvc/llvm-project?rev=320746&view=rev
Log:
DAG: Expose all MMO flags in getTgtMemIntrinsic
Rather than adding more bits to express every
MMO flag you could want, just directly use the
MMO flags. Also fixes using a bunch of bool arguments to
getMemIntrinsicNode.
On AMDGPU, buffer and image intrinsics should always
have MODereferencable set, but currently there is no
way to do that directly during the initial intrinsic
lowering.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Dec 14 13:39:51 2017
@@ -988,11 +988,14 @@ public:
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
/// less than FIRST_TARGET_MEMORY_OPCODE.
- SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
- ArrayRef<SDValue> Ops, EVT MemVT,
- MachinePointerInfo PtrInfo, unsigned Align = 0,
- bool Vol = false, bool ReadMem = true,
- bool WriteMem = true, unsigned Size = 0);
+ SDValue getMemIntrinsicNode(
+ unsigned Opcode, const SDLoc &dl, SDVTList VTList,
+ ArrayRef<SDValue> Ops, EVT MemVT,
+ MachinePointerInfo PtrInfo,
+ unsigned Align = 0,
+ MachineMemOperand::Flags Flags
+ = MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
+ unsigned Size = 0);
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
ArrayRef<SDValue> Ops, EVT MemVT,
Modified: llvm/trunk/include/llvm/CodeGen/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLowering.h?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h Thu Dec 14 13:39:51 2017
@@ -707,10 +707,8 @@ public:
unsigned size = 0; // the size of the memory location
// (taken from memVT if zero)
unsigned align = 1; // alignment
- bool vol = false; // is volatile?
- bool readMem = false; // reads memory?
- bool writeMem = false; // writes memory?
+ MachineMemOperand::Flags flags = MachineMemOperand::MONone;
IntrinsicInfo() = default;
};
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Dec 14 13:39:51 2017
@@ -852,13 +852,9 @@ bool IRTranslator::translateCall(const U
TargetLowering::IntrinsicInfo Info;
// TODO: Add a GlobalISel version of getTgtMemIntrinsic.
if (TLI.getTgtMemIntrinsic(Info, CI, ID)) {
- MachineMemOperand::Flags Flags =
- Info.vol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
- Flags |=
- Info.readMem ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore;
uint64_t Size = Info.memVT.getStoreSize();
MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
- Flags, Size, Info.align));
+ Info.flags, Size, Info.align));
}
return true;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Dec 14 13:39:51 2017
@@ -5777,21 +5777,15 @@ SDValue SelectionDAG::getMergeValues(Arr
SDValue SelectionDAG::getMemIntrinsicNode(
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
- EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol,
- bool ReadMem, bool WriteMem, unsigned Size) {
+ EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align,
+ MachineMemOperand::Flags Flags, unsigned Size) {
if (Align == 0) // Ensure that codegen never sees alignment 0
Align = getEVTAlignment(MemVT);
- MachineFunction &MF = getMachineFunction();
- auto Flags = MachineMemOperand::MONone;
- if (WriteMem)
- Flags |= MachineMemOperand::MOStore;
- if (ReadMem)
- Flags |= MachineMemOperand::MOLoad;
- if (Vol)
- Flags |= MachineMemOperand::MOVolatile;
if (!Size)
Size = MemVT.getStoreSize();
+
+ MachineFunction &MF = getMachineFunction();
MachineMemOperand *MMO =
MF.getMachineMemOperand(PtrInfo, Flags, Size, Align);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Dec 14 13:39:51 2017
@@ -4240,11 +4240,10 @@ void SelectionDAGBuilder::visitTargetInt
SDValue Result;
if (IsTgtIntrinsic) {
// This is target intrinsic that touches memory
- Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
- VTs, Ops, Info.memVT,
- MachinePointerInfo(Info.ptrVal, Info.offset),
- Info.align, Info.vol,
- Info.readMem, Info.writeMem, Info.size);
+ Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
+ Ops, Info.memVT,
+ MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
+ Info.flags, Info.size);
} else if (!HasChain) {
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
} else if (!I.getType()->isVoidTy()) {
@@ -5823,6 +5822,7 @@ SelectionDAGBuilder::visitIntrinsicCall(
case Intrinsic::prefetch: {
SDValue Ops[5];
unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
+ auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
Ops[0] = getRoot();
Ops[1] = getValue(I.getArgOperand(0));
Ops[2] = getValue(I.getArgOperand(1));
@@ -5833,9 +5833,7 @@ SelectionDAGBuilder::visitIntrinsicCall(
EVT::getIntegerVT(*Context, 8),
MachinePointerInfo(I.getArgOperand(0)),
0, /* align */
- false, /* volatile */
- rw==0, /* read */
- rw==1)); /* write */
+ Flags));
return nullptr;
}
case Intrinsic::lifetime_start:
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -7393,9 +7393,8 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
Info.offset = 0;
Info.align = 0;
- Info.vol = false; // volatile loads with NEON intrinsics not supported
- Info.readMem = true;
- Info.writeMem = false;
+ // volatile loads with NEON intrinsics not supported
+ Info.flags = MachineMemOperand::MOLoad;
return true;
}
case Intrinsic::aarch64_neon_st2:
@@ -7420,9 +7419,8 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
Info.offset = 0;
Info.align = 0;
- Info.vol = false; // volatile stores with NEON intrinsics not supported
- Info.readMem = false;
- Info.writeMem = true;
+ // volatile stores with NEON intrinsics not supported
+ Info.flags = MachineMemOperand::MOStore;
return true;
}
case Intrinsic::aarch64_ldaxr:
@@ -7433,9 +7431,7 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
- Info.vol = true;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true;
}
case Intrinsic::aarch64_stlxr:
@@ -7446,9 +7442,7 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(1);
Info.offset = 0;
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
- Info.vol = true;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true;
}
case Intrinsic::aarch64_ldaxp:
@@ -7458,9 +7452,7 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = 16;
- Info.vol = true;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true;
case Intrinsic::aarch64_stlxp:
case Intrinsic::aarch64_stxp:
@@ -7469,9 +7461,7 @@ bool AArch64TargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(2);
Info.offset = 0;
Info.align = 16;
- Info.vol = true;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true;
default:
break;
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -566,11 +566,12 @@ bool SITargetLowering::getTgtMemIntrinsi
Info.memVT = MVT::getVT(CI.getType());
Info.ptrVal = CI.getOperand(0);
Info.align = 0;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
- Info.vol = !Vol || !Vol->isZero();
- Info.readMem = true;
- Info.writeMem = true;
+ if (!Vol || !Vol->isZero())
+ Info.flags |= MachineMemOperand::MOVolatile;
+
return true;
}
default:
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -13606,9 +13606,8 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.offset = 0;
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
- Info.vol = false; // volatile loads with NEON intrinsics not supported
- Info.readMem = true;
- Info.writeMem = false;
+ // volatile loads with NEON intrinsics not supported
+ Info.flags = MachineMemOperand::MOLoad;
return true;
}
case Intrinsic::arm_neon_vst1:
@@ -13633,9 +13632,8 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.offset = 0;
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
- Info.vol = false; // volatile stores with NEON intrinsics not supported
- Info.readMem = false;
- Info.writeMem = true;
+ // volatile stores with NEON intrinsics not supported
+ Info.flags = MachineMemOperand::MOStore;
return true;
}
case Intrinsic::arm_ldaex:
@@ -13647,9 +13645,7 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
- Info.vol = true;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true;
}
case Intrinsic::arm_stlex:
@@ -13661,9 +13657,7 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.ptrVal = I.getArgOperand(1);
Info.offset = 0;
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
- Info.vol = true;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true;
}
case Intrinsic::arm_stlexd:
@@ -13673,9 +13667,7 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.ptrVal = I.getArgOperand(2);
Info.offset = 0;
Info.align = 8;
- Info.vol = true;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true;
case Intrinsic::arm_ldaexd:
@@ -13685,9 +13677,7 @@ bool ARMTargetLowering::getTgtMemIntrins
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = 8;
- Info.vol = true;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true;
default:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -2282,9 +2282,9 @@ bool HexagonTargetLowering::getTgtMemInt
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
- Info.vol = true;
- Info.readMem = true;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOLoad |
+ MachineMemOperand::MOStore |
+ MachineMemOperand::MOVolatile;
return true;
}
default:
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -1561,8 +1561,7 @@ SDValue NVPTXTargetLowering::LowerCall(T
Chain = DAG.getMemIntrinsicNode(
Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
TheStoreType, MachinePointerInfo(), EltAlign,
- /* Volatile */ false, /* ReadMem */ false,
- /* WriteMem */ true, /* Size */ 0);
+ MachineMemOperand::MOStore);
InFlag = Chain.getValue(1);
// Cleanup.
@@ -1623,8 +1622,7 @@ SDValue NVPTXTargetLowering::LowerCall(T
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
CopyParamOps, elemtype,
MachinePointerInfo(), /* Align */ 0,
- /* Volatile */ false, /* ReadMem */ false,
- /* WriteMem */ true, /* Size */ 0);
+ MachineMemOperand::MOStore);
InFlag = Chain.getValue(1);
}
@@ -1810,8 +1808,8 @@ SDValue NVPTXTargetLowering::LowerCall(T
DAG.getConstant(Offsets[VecIdx], dl, MVT::i32), InFlag};
SDValue RetVal = DAG.getMemIntrinsicNode(
Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
- MachinePointerInfo(), EltAlign, /* Volatile */ false,
- /* ReadMem */ true, /* WriteMem */ false, /* Size */ 0);
+ MachinePointerInfo(), EltAlign,
+ MachineMemOperand::MOLoad);
for (unsigned j = 0; j < NumElts; ++j) {
SDValue Ret = RetVal.getValue(j);
@@ -2596,8 +2594,7 @@ NVPTXTargetLowering::LowerReturn(SDValue
Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
StoreOperands, TheStoreType,
MachinePointerInfo(), /* Align */ 1,
- /* Volatile */ false, /* ReadMem */ false,
- /* WriteMem */ true, /* Size */ 0);
+ MachineMemOperand::MOStore);
// Cleanup vector state.
StoreOperands.clear();
}
@@ -3328,8 +3325,9 @@ bool NVPTXTargetLowering::getTgtMemIntri
// in order to model data exchange with other threads, but perform no real
// memory accesses.
Info.memVT = MVT::i1;
- Info.readMem = true; // Our result depends on other thread's arguments.
- Info.writeMem = true; // Other threads depend on our thread's argument.
+
+ // Our result depends on both our and other thread's arguments.
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
return true;
case Intrinsic::nvvm_wmma_load_a_f16_col:
case Intrinsic::nvvm_wmma_load_a_f16_row:
@@ -3359,9 +3357,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v8f16;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
}
@@ -3382,9 +3378,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v4f16;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
}
@@ -3405,9 +3399,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v8f32;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
}
@@ -3428,9 +3420,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v4f16;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore;
Info.align = 16;
return true;
}
@@ -3451,9 +3441,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v8f32;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore;
Info.align = 16;
return true;
}
@@ -3490,9 +3478,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = getValueType(DL, I.getType());
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
Info.align = 0;
return true;
}
@@ -3510,9 +3496,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = getValueType(DL, I.getType());
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
return true;
@@ -3531,9 +3515,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = getValueType(DL, I.getType());
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
return true;
@@ -3599,9 +3581,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v4f32;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
@@ -3721,9 +3701,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::v4i32;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
@@ -3776,9 +3754,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::i8;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
@@ -3831,9 +3807,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::i16;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
@@ -3886,9 +3860,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::i32;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
@@ -3926,9 +3898,7 @@ bool NVPTXTargetLowering::getTgtMemIntri
Info.memVT = MVT::i64;
Info.ptrVal = nullptr;
Info.offset = 0;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
Info.align = 16;
return true;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -2428,8 +2428,8 @@ static SDValue getTOCEntry(SelectionDAG
SDValue Ops[] = { GA, Reg };
return DAG.getMemIntrinsicNode(
PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
- MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
- false, 0);
+ MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
+ MachineMemOperand::MOLoad);
}
SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
@@ -13347,9 +13347,7 @@ bool PPCTargetLowering::getTgtMemIntrins
Info.offset = -VT.getStoreSize()+1;
Info.size = 2*VT.getStoreSize()-1;
Info.align = 1;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
return true;
}
case Intrinsic::ppc_qpx_qvlfda:
@@ -13383,9 +13381,7 @@ bool PPCTargetLowering::getTgtMemIntrins
Info.offset = 0;
Info.size = VT.getStoreSize();
Info.align = 1;
- Info.vol = false;
- Info.readMem = true;
- Info.writeMem = false;
+ Info.flags = MachineMemOperand::MOLoad;
return true;
}
case Intrinsic::ppc_qpx_qvstfd:
@@ -13437,9 +13433,7 @@ bool PPCTargetLowering::getTgtMemIntrins
Info.offset = -VT.getStoreSize()+1;
Info.size = 2*VT.getStoreSize()-1;
Info.align = 1;
- Info.vol = false;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore;
return true;
}
case Intrinsic::ppc_qpx_qvstfda:
@@ -13472,9 +13466,7 @@ bool PPCTargetLowering::getTgtMemIntrins
Info.offset = 0;
Info.size = VT.getStoreSize();
Info.align = 1;
- Info.vol = false;
- Info.readMem = false;
- Info.writeMem = true;
+ Info.flags = MachineMemOperand::MOStore;
return true;
}
default:
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=320746&r1=320745&r2=320746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 14 13:39:51 2017
@@ -4490,9 +4490,7 @@ bool X86TargetLowering::getTgtMemIntrins
return false;
Info.opc = ISD::INTRINSIC_W_CHAIN;
- Info.readMem = false;
- Info.writeMem = false;
- Info.vol = false;
+ Info.flags = MachineMemOperand::MONone;
Info.offset = 0;
switch (IntrData->Type) {
@@ -4500,14 +4498,14 @@ bool X86TargetLowering::getTgtMemIntrins
Info.ptrVal = I.getArgOperand(0);
Info.memVT = MVT::getVT(I.getType());
Info.align = 1;
- Info.readMem = true;
+ Info.flags |= MachineMemOperand::MOLoad;
break;
}
case COMPRESS_TO_MEM: {
Info.ptrVal = I.getArgOperand(0);
Info.memVT = MVT::getVT(I.getArgOperand(1)->getType());
Info.align = 1;
- Info.writeMem = true;
+ Info.flags |= MachineMemOperand::MOStore;
break;
}
case TRUNCATE_TO_MEM_VI8:
@@ -4525,7 +4523,7 @@ bool X86TargetLowering::getTgtMemIntrins
Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
Info.align = 1;
- Info.writeMem = true;
+ Info.flags |= MachineMemOperand::MOStore;
break;
}
default:
@@ -6660,8 +6658,7 @@ static SDValue EltsFromConsecutiveLoads(
DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, VecSVT,
LDBase->getPointerInfo(),
LDBase->getAlignment(),
- false/*isVolatile*/, true/*ReadMem*/,
- false/*WriteMem*/);
+ MachineMemOperand::MOLoad);
for (auto *LD : Loads)
DAG.makeEquivalentMemoryOrdering(LD, ResNode);
return DAG.getBitcast(VT, ResNode);
@@ -19354,13 +19351,12 @@ SDValue X86TargetLowering::LowerVAARG(SD
DAG.getConstant(ArgMode, dl, MVT::i8),
DAG.getConstant(Align, dl, MVT::i32)};
SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
- SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
- VTs, InstOps, MVT::i64,
- MachinePointerInfo(SV),
- /*Align=*/0,
- /*Volatile=*/false,
- /*ReadMem=*/true,
- /*WriteMem=*/true);
+ SDValue VAARG = DAG.getMemIntrinsicNode(
+ X86ISD::VAARG_64, dl,
+ VTs, InstOps, MVT::i64,
+ MachinePointerInfo(SV),
+ /*Align=*/0,
+ MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
Chain = VAARG.getValue(1);
// Load the next argument and return it
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