[llvm] r320736 - [SLPVectorizer] Don't ignore scalar extraction instructions of aggregate value
Guozhi Wei via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 11:35:43 PST 2017
Author: carrot
Date: Thu Dec 14 11:35:43 2017
New Revision: 320736
URL: http://llvm.org/viewvc/llvm-project?rev=320736&view=rev
Log:
[SLPVectorizer] Don't ignore scalar extraction instructions of aggregate value
In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted.
For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation.
Differential Revision: https://reviews.llvm.org/D41139
Added:
llvm/trunk/test/Transforms/SLPVectorizer/PowerPC/aggregate.ll
llvm/trunk/test/Transforms/SLPVectorizer/X86/aggregate.ll
Modified:
llvm/trunk/include/llvm/Transforms/Vectorize/SLPVectorizer.h
llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp
Modified: llvm/trunk/include/llvm/Transforms/Vectorize/SLPVectorizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Vectorize/SLPVectorizer.h?rev=320736&r1=320735&r2=320736&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Vectorize/SLPVectorizer.h (original)
+++ llvm/trunk/include/llvm/Transforms/Vectorize/SLPVectorizer.h Thu Dec 14 11:35:43 2017
@@ -96,11 +96,13 @@ private:
/// \brief Try to vectorize a list of operands.
/// \@param BuildVector A list of users to ignore for the purpose of
- /// scheduling and that don't need extracting.
+ /// scheduling and cost estimation when NeedExtraction
+ /// is false.
/// \returns true if a value was vectorized.
bool tryToVectorizeList(ArrayRef<Value *> VL, slpvectorizer::BoUpSLP &R,
ArrayRef<Value *> BuildVector = None,
- bool AllowReorder = false);
+ bool AllowReorder = false,
+ bool NeedExtraction = false);
/// \brief Try to vectorize a chain that may start at the operands of \p I.
bool tryToVectorize(Instruction *I, slpvectorizer::BoUpSLP &R);
Modified: llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp?rev=320736&r1=320735&r2=320736&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp Thu Dec 14 11:35:43 2017
@@ -4533,7 +4533,8 @@ bool SLPVectorizerPass::tryToVectorizePa
bool SLPVectorizerPass::tryToVectorizeList(ArrayRef<Value *> VL, BoUpSLP &R,
ArrayRef<Value *> BuildVector,
- bool AllowReorder) {
+ bool AllowReorder,
+ bool NeedExtraction) {
if (VL.size() < 2)
return false;
@@ -4627,11 +4628,12 @@ bool SLPVectorizerPass::tryToVectorizeLi
<< "\n");
ArrayRef<Value *> Ops = VL.slice(I, OpsWidth);
+ ArrayRef<Value *> EmptyArray;
ArrayRef<Value *> BuildVectorSlice;
if (!BuildVector.empty())
BuildVectorSlice = BuildVector.slice(I, OpsWidth);
- R.buildTree(Ops, BuildVectorSlice);
+ R.buildTree(Ops, NeedExtraction ? EmptyArray : BuildVectorSlice);
// TODO: check if we can allow reordering for more cases.
if (AllowReorder && R.shouldReorder()) {
// Conceptually, there is nothing actually preventing us from trying to
@@ -5821,7 +5823,9 @@ bool SLPVectorizerPass::vectorizeInsertV
return false;
DEBUG(dbgs() << "SLP: array mappable to vector: " << *IVI << "\n");
- return tryToVectorizeList(BuildVectorOpds, R, BuildVector, false);
+ // Aggregate value is unlikely to be processed in vector register, we need to
+ // extract scalars into scalar registers, so NeedExtraction is set true.
+ return tryToVectorizeList(BuildVectorOpds, R, BuildVector, false, true);
}
bool SLPVectorizerPass::vectorizeInsertElementInst(InsertElementInst *IEI,
Added: llvm/trunk/test/Transforms/SLPVectorizer/PowerPC/aggregate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/PowerPC/aggregate.ll?rev=320736&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SLPVectorizer/PowerPC/aggregate.ll (added)
+++ llvm/trunk/test/Transforms/SLPVectorizer/PowerPC/aggregate.ll Thu Dec 14 11:35:43 2017
@@ -0,0 +1,19 @@
+; RUN: opt -S -mtriple=powerpc64-linux-gnu -mcpu=pwr9 -mattr=+vsx -slp-vectorizer < %s | FileCheck %s
+
+%struct.S = type { i8*, i8* }
+
+ at kS0 = common global %struct.S zeroinitializer, align 8
+
+define { i64, i64 } @getS() {
+entry:
+ %0 = load i64, i64* bitcast (%struct.S* @kS0 to i64*), align 8
+ %1 = load i64, i64* bitcast (i8** getelementptr inbounds (%struct.S, %struct.S* @kS0, i64 0, i32 1) to i64*), align 8
+ %2 = insertvalue { i64, i64 } undef, i64 %0, 0
+ %3 = insertvalue { i64, i64 } %2, i64 %1, 1
+ ret { i64, i64 } %3
+}
+
+; CHECK: load i64
+; CHECK-NOT: load <2 x i64>
+; CHECK-NOT: extractelement
+
Added: llvm/trunk/test/Transforms/SLPVectorizer/X86/aggregate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/X86/aggregate.ll?rev=320736&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SLPVectorizer/X86/aggregate.ll (added)
+++ llvm/trunk/test/Transforms/SLPVectorizer/X86/aggregate.ll Thu Dec 14 11:35:43 2017
@@ -0,0 +1,19 @@
+; RUN: opt -S -mtriple=x86_64-unknown-linux -mcpu=corei7 -slp-vectorizer < %s | FileCheck %s
+
+%struct.S = type { i8*, i8* }
+
+ at kS0 = common global %struct.S zeroinitializer, align 8
+
+define { i64, i64 } @getS() {
+entry:
+ %0 = load i64, i64* bitcast (%struct.S* @kS0 to i64*), align 8
+ %1 = load i64, i64* bitcast (i8** getelementptr inbounds (%struct.S, %struct.S* @kS0, i64 0, i32 1) to i64*), align 8
+ %2 = insertvalue { i64, i64 } undef, i64 %0, 0
+ %3 = insertvalue { i64, i64 } %2, i64 %1, 1
+ ret { i64, i64 } %3
+}
+
+; CHECK: load i64
+; CHECK-NOT: load <2 x i64>
+; CHECK-NOT: extractelement
+
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